EP2C8 datasheet(22/36 Pages) ALTERA

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Pin Description

Enhanced Configuration (EPC) Devices Datasheet

January 2012

Altera Corporation

Pin Description

Table 8 through Table 10 list the EPC device pins. These tables include configuration

interface pins, external flash interface pins, JTAG interface pins, and other pins.

Table 8. Configuration Interface Pins

Pin Name

Pin Type

Description

DATA[7..0]

Output

Configuration data output bus. DATA changes on each falling edge of DCLK . DATA

is latched into the FPGA on the rising edge of DCLK.

DCLK

Output

The DCLK output pin from the EPC device serves as the FPGA configuration clock.

DATA

is latched by the FPGA on the rising edge of DCLK.

nCS

Input

The nCS pin is an input to the EPC device and is connected to the FPGA’s

CONF

_DONE signal for error detection after all configuration data is transmitted to

the FPGA. The FPGA will always drive nCS and OE low when nCONFIG is asserted.

This pin contains a programmable internal weak pull-up resistor of 6 K

 that can

be disabled or enabled in the Quartus II software through the Disable nCS and

OE pull-ups on configuration device option.

nINIT_CONF

Open-Drain Output

The nINIT_CONF pin can be connected to the nCONFIG pin on the FPGA to

initiate configuration from the EPC device using a private JTAG instruction. This

pin contains an internal weak pull-up resistor of 6K

that is always active. The

INIT

_CONF pin does not need to be connected if its functionality is not used. If

INIT

_CONF is not used, nCONFIG must be pulled to VCC either directly or

through a pull-up resistor.

Open-Drain

Bidirectional

This pin is driven low when POR is not complete. A user-selectable 2-ms or

100-ms counter holds off the release of OE during initial power up to permit

voltage levels to stabilize. POR time can be extended by externally holding OE low.

is connected to the FPGA nSTATUS signal. After the EPC device controller

releases OE, it waits for the nSTATUS-OE line to go high before starting the FPGA

configuration process. This pin contains a programmable internal weak pull-up

resistor of 6 K

that can be disabled or enabled in the Quartus II software

through the Disable nCS and OE pull-ups on configuration device option.

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