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STA335W датащи(PDF) 18 Page - STMicroelectronics |
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STA335W датащи(HTML) 18 Page - STMicroelectronics |
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18 / 43 page ![]() Register description STA335W 18/43 5.1.1 Master clock select The STA335W supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: ● 32.768 MHz for 32 kHz ● 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz ● 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. Table 10. Master clock select Bit R/W RST Name Description 0R/W 1 MCS0 Selects the ratio between the input I2S sample frequency and the input clock. 1R/W 1 MCS1 2R/W 0 MCS2 Table 11. Input sampling rates Input sample rate fs (kHz) IR MCS[2:0] 101 100 011 010 001 000 32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs 88.2, 96 01 NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs 176.4, 192 1X NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs |
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