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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M68HC08 датащи(PDF) 104 Page - Freescale Semiconductor, Inc |
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M68HC08 датащи(HTML) 104 Page - Freescale Semiconductor, Inc |
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104 / 332 page  System Integration Module (SIM) Technical Data MC68HC908JB16 — Rev. 1.1 104 System Integration Module (SIM) Freescale Semiconductor 8.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 OSCDCLK cycles. Sixty-four OSCDCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: • A POR pulse is generated. • The internal reset signal is asserted. • The SIM enables the oscillator to drive OSCDCLK. • Internal clocks to the CPU and modules are held inactive for 4096 OSCDCLK cycles to allow stabilization of the oscillator. • The RST pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. Figure 8-7. POR Recovery PORRST OSC1 OSCDCLK OSCOUT RST IAB 4096 CYCLES 32 CYCLES 32 CYCLES $FFFE $FFFF |
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