M68HC08 datasheet(98/332 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908JB16 — Rev. 1.1

System Integration Module (SIM)

Freescale Semiconductor

8.6.5

Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 114

8.7

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

8.7.1

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

8.7.2

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

8.8

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

8.8.1

SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 118

8.8.2

SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 119

8.8.3

SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 120

8.2 Introduction

This section describes the system integration module (SIM). Together

with the CPU, the SIM controls all MCU activities. The SIM is a system

state controller that coordinates CPU and exception timing. A block

diagram of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of

the SIM I/O registers. The SIM is responsible for:

•

Bus clock generation and control for CPU and peripherals

–

Stop/wait/reset/break entry and recovery

–

Internal clock control

•

Master reset control, including power-on reset (POR) and COP

timeout

•

Interrupt control:

–

Acknowledge timing

–

Arbitration control timing

–

Vector address generation

•

CPU enable/disable timing

•

Modular architecture expandable to 128 interrupt sources

Table 8-1 shows the internal signal names used in this section.

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