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LP38798 датащи(PDF) 16 Page - Texas Instruments

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номер детали LP38798
подробное описание детали  LP38798-ADJ High PSRR, Ultra Low Noise, 800 mA Linear Voltage Regulator for RF/Analog Circuits
PDF  23 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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LP38798 датащи(HTML) 16 Page - Texas Instruments

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LP38798
SNOSCT6A – MARCH 2013 – REVISED MAY 2013
www.ti.com
The thermal dissipation of the 12-lead WSON package is directly related to the printed circuit board construction
and the amount of additional copper area connected to the DAP.
The DAP (exposed pad) on the bottom of the 12-lead WSON DNT0012B package is connected to the die
substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the
twelve pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is
strongly recommend that the DAP be connected directly to the ground at device leads 6 and 7 (i.e. GND).
Alternately, but not recommended, the DAP may be left floating (i.e. no electrical connection). The DAP must not
be connected to any potential other than ground.
For the LP38798SD in the 12-Lead WSON DNT0012B package, the junction-to-case thermal resistance rating,
θJC, is 5°C/W, where the case is defined as being on the bottom of the package at the center of the DAP.
The junction-to-ambient thermal performance,
θJA, for the LP38798SD in the 12-lead WSON DNT0012B
package, using the JEDEC JESD51 standards, is summarized in the following table:
LP38798SD-ADJ (12-lead WSON DNT0012B) Thermal Performance
Board
Thermal
θJA
ΨJB
θJC
Type
Vias
JEDEC
2-Layer
None
138°C/W
45.9°C/W
5°C/W
JESD 51-3
1
51°C/W
26.1°C/W
2
45°C/W
24.7°C/W
JEDEC
4-Layer
4
39°C/W
18.0°C/W
5°C/W
JESD 51-7
6
36°C/W
14.9°C/W
8
34°C/W
13.2°C/W
Estimating the Junction Temperature
The EIA/JEDEC standard (JESD51-2) provides methodologies to estimate the junction temperature from external
measurements (
ΨJB references the temperature at the PCB, and ΨJT references the temperature at the top
surface of the package) when operating under steady-state power dissipation conditions. These methodologies
have been determined to be relatively independent of the copper thermal spreading area that may be attached to
the package DAP when compared to the more typical
θJA. Refer to ' Application Report : Semiconductor and IC
Package Thermal Metrics' , Literature Number SPRA953B, for specifics.
Board Layout
The dynamic performance of the LP38798 is dependant on the layout of the PCB. PCB layout practices that are
adequate for typical LDO's may degrade the PSRR, noise, or transient performance of the LP38798.
Best performance is achieved by placing all of the components on the same side of the PCB as the LP38798,
and as close as is practical to the LP38798 package. All component ground connections should be back to the
LP38798 analog ground connection using as wide, and as short, of a copper trace as is practical. The connection
from the FB pin to the VSET resistors must be as short as possible as the FB pin is a high impedance input. Any
trace length on the FB pin will act as an antenna.
Connections using long trace lengths, narrow trace widths, and connections through vias should be avoided.
These will add parasitic inductances and resistance that results in inferior performance especially during transient
conditions.
A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly
recommended. This Ground Plane serves two purposes : 1) Provide a circuit reference plane to assure accuracy,
and 2) provides a thermal plane to remove heat from the LP38798 through thermal vias under the package DAP.
16
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP38798



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