Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

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Figure 4. Main PWM Comparator Block Diagram

FB_

REF

CSH_

CSL_

SLOPE COMPENSATION

VL

I1

R1

R2

TO PWM

LOGIC

OUTPUT DRIVER

UNCOMPENSATED

HIGH-SPEED

LEVEL TRANSLATOR

AND BUFFER

I2

I3

current value as a function of the output-voltage error

signal. In continuous-conduction mode, the average

inductor current is nearly the same as the peak current,

so the circuit acts as a switch-mode transconductance

amplifier. This pushes the second output LC filter pole,

normally found in a duty-factor-controlled (voltage-

mode) PWM, to a higher frequency. To preserve inner-

loop stability and eliminate regenerative inductor

current “staircasing,” a slope compensation ramp is

summed into the main PWM comparator to make the

apparent duty factor less than 50%.

The MAX1630A family uses a relatively low loop gain,

allowing the use of lower cost output capacitors. The rel-

ative gains of the voltage-sense and current-sense

inputs are weighted by the values of current sources

that bias three differential input stages in the main PWM

comparator (Figure 4). The relative gain of the voltage

comparator to the current comparator is internally fixed

at K = 2:1. The low loop gain results in the 2% typical

load-regulation error. The low value of loop gain helps

reduce output filter capacitor size and cost by shifting

the unity-gain crossover frequency to a lower level.

The output filter capacitors (Figure 1, C1 and C2) set a

dominant pole in the feedback loop that must roll off the

loop gain to unity before encountering the zero intro-

duced by the output capacitor’s parasitic resistance

(ESR) (see the Design Procedure section). A 60kHz

pole-zero cancellation filter provides additional rolloff

above the unity-gain crossover. This internal 60kHz low-

pass compensation filter cancels the zero due to filter

capacitor ESR. The 60kHz filter is included in the loop in

both fixed-output and adjustable-output modes.

Synchronous Rectifier Driver (DL)

Synchronous rectification reduces conduction losses in

the rectifier by shunting the normal Schottky catch diode

with a low-resistance MOSFET switch. Also, the synchro-

nous rectifier ensures proper startup of the boost gate-

driver circuit. If the synchronous power MOSFETs are

omitted for cost or other reasons, replace them with a

small-signal MOSFET, such as a 2N7002.

If the circuit is operating in continuous-conduction mode,

the DL drive waveform is the complement of the DH high-

side drive waveform (with controlled dead time to prevent

cross-conduction or “shoot-through”). In discontinuous

(light-load) mode, the synchronous switch is turned off as

the inductor current falls through zero. The synchronous

rectifier works under all operating conditions, including

Idle Mode. The SECFB signal further controls the syn-

chronous switch timing to improve multiple-output cross-

regulation (see the Secondary Feedback Regulation

Loop section).