AD7849

REV. B

–13–

DSP56000

SCK

STD

SC2

AD7849*

LDAC

SCLK

SDIN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

TIMER

Figure 21. AD7849 to DSP56000 Interface

AD7849-TMS320C2x Interface

Figure 22 shows a serial interface between the AD7849 and the

TMS320C2x DSP processor. In this interface, the CLKX and

FSX signals for the TMS320C2x should be generated using

external clock/timer circuitry. The FSX pin of the TMS320C2x

must be configured as an input. Data from the TMS320C2x is

valid on the falling edge of CLKX.

TMS320C2x

FSX

CLKX

DX

AD7849*

LDAC

SCLK

SDIN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

CLOCK/TIMER

Figure 22. AD7849 to TMS320C2x Interface

The clock/timer circuitry generates the

LDAC signal for the

AD7849 to synchronize the update of the output with the serial

transmission. Alternatively, the automatic update mode may be

selected by connecting

LDAC to DGND.

AD7849-68HC11 Interface

Figure 23 shows a serial interface between the AD7849 and the

68HC11 microcontroller. SCK of the 68HC11 drives SCLK of

the AD7849 while the MOSI output drives the serial data line

of the AD7849. The

SYNC signal is derived from a port line

(PC0 shown).

For correct operation of this interface, the 68HC11 should be

configured such that its CPOL bit is a 0 and its CPHA bit is a 1.

When data is to be transmitted to the part, PC0 is taken low.

When the 68HC11 is configured like this, data on MOSI is valid

on the falling edge of SCK. The 68HC11 transmits its serial

data in 8-bit bytes with only eight falling clock edges occurring

in the transmit cycle. To load data to the AD7849, PC0 is left

low after the first eight bits are transferred and a second byte of

data is then transferred serially to the AD7849. When the sec-

ond serial transfer is complete, the PC0 line is taken high.

Figure 23 shows the

LDAC input of the AD7849 being driven

from another bit programmable port line (PC1). As a result, the

DAC can be updated by taking

LDAC low after the DAC input

register has been loaded.

68HC11*

PC0

SCK

MOSI

PC1

AD7849*

LDAC

SCLK

SDIN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 23. AD7849 to 68HC11 Interface

AD7849-87C51 Interface

A serial interface between the AD7849 and the 87C51 micro-

controller is shown in Figure 24. TXD of the 87C51 drives

SCLK of the AD7849 while RXD drives the serial data line of

the part. The

SYNC signal is derived from the port line P3.3

and the

LDAC line is driven port line P3.2.

The 87C51 provides the LSB of its SBUF register as the first bit

in the serial data stream. Therefore, the user will have to ensure

that the data in the SBUF register is arranged correctly so that

the most significant bits are the first to be transmitted to the

AD7849 and the last bit to be sent is the LSB of the word to be

loaded to the AD7849. When data is to be transmitted to the

part, P3.3 is taken low. Data on RXD is valid on the falling

edge of TXD. The 87C51 transmits its serial data in 8-bit bytes

with only eight falling clock edges occurring in the transmit

cycle. To load data to the AD7849, P3.3 is left low after the

first eight bits are transferred and a second byte of data is then

transferred serially to the AD7849. When the second serial

transfer is complete, the P3.3 line is taken high.

Figure 24 shows the

LDAC input of the AD7849 driven from

the bit programmable port line P3.2. As a result, the DAC out-

put can be updated by taking the

LDAC line low following the

completion of the write cycle. Alternatively

LDAC could be

hardwired low and the analog output will be updated on the

sixteenth falling edge of TXD after the

SYNC signal for the

DAC has gone low.

87C51*

P3.3

TXD

RXD

P3.2

AD7849*

LDAC

SCLK

SDIN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 24. AD7849 to 87C51 Interface