SPC5604BF2MLL6 datasheet(55/109 Pages) FREESCALE

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Package pinouts and signal descriptions

MPC5604B/C Microcontroller Data Sheet, Rev. 11

Freescale Semiconductor

Example 1. No regulator (worst case)

The

VDD(STDBY)| parameter can be seen as the VDD voltage drop through the ESR resistance of the regulator stability

capacitor when the IDD_BV current required to load VDD_LV domain during the standby exit. It is thus possible to define the

maximum equivalent resistance ESRSTDBY(MAX) of the total capacitance on the VDD supply:

ESRSTDBY(MAX) = VDD(STDBY)|/IDD_BV = (30 mV)/(300 mA) = 0.1 1

The dVDD(STDBY)/dt parameter can be seen as the VDD voltage drop at the capacitance pin (excluding ESR drop) while

providing the IDD_BV supply required to load VDD_LV domain during the standby exit. It is thus possible to define the minimum

equivalent capacitance CSTDBY(MIN) of the total capacitance on the VDD supply:

CSTDBY(MIN) = IDD_BV/dVDD(STDBY)/dt = (300 mA)/(15 mV/µs) = 20 µF

This configuration is a worst case, with the assumption no regulator is available.

Example 2. Simplified regulator

The regulator should be able to provide significant amount of the current during the standby exit process. For example, in case

of an ideal voltage regulator providing 200 mA current, it is possible to recalculate the equivalent ESRSTDBY(MAX) and

CSTDBY(MIN) as follows:

ESRSTDBY(MAX) = VDD(STDBY)|/(IDD_BV  200 mA) = (30 mV)/(100 mA) = 0.3 

CSTDBY(MIN) = (IDD_BV  200 mA)/dVDD(STDBY)/dt = (300 mA  200 mA)/(15 mV/µs) = 6.7 µF

In case optimization is required, CSTDBY(MIN) and ESRSTDBY(MAX) should be calculated based on the regulator

characteristics as well as the board VDD plane characteristics.

3.17.2

Low voltage detector electrical characteristics

The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage

detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied:

•

POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state (refer to RGM

Destructive Event Status (RGM_DES) Register flag F_POR in device reference manual)

•

LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer to RGM Destructive Event

Status (RGM_DES) Register flag F_LVD27 in device reference manual)

•

LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to RGM Functional Event Status

(RGM_FES) Register flag F_LVD45 in device reference manual)

•

LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES) Register flag

F_LVD12_PD1 in device reference manual

•

LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES) Register flag

F_LVD12_PD0 in device reference manual)

NOTE

When enabled, power domain No. 2 is monitored through LVDLVBKP.

1. Based on typical time for standby exit sequence of 20 µs, ESR(MIN) can actually be considered at ~50 kHz.

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