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DAC8420FSZ2 датащи(PDF) 9 Page - Analog Devices |
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DAC8420FSZ2 датащи(HTML) 9 Page - Analog Devices |
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9 / 24 page ![]() DAC8420 Rev. B | Page 9 of 24 Table 6. Control Function Logic Table CLK1 CS1 LD CLR CLSEL Serial Input Shift Register DAC Register A to DAC Register D NC2 High High Low High No change Loads midscale value (0x800) NC2 High High Low Low No change Loads zero-scale value (0x000) NC2 High High ↑ High /Low No change Latches value ↑ Low High High NC2 Shifts register one bit No change Low ↑ High High NC2 Shifts register one bit No change High NC ( ↑)2 ↓ High NC2 No change Loads the serial data-word3 High NC2 Low High NC2 No change Transparent4 NC2 High High High NC2 No change No change 1 CLK and CS are interchangeable. 2 NC = Don’t Care. 3 Returning CS high while CLK is high avoids an additional false clock of serial input data. CLK and CS are interchangeable. 4 Do not clock in serial data while LD is low. |
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