DAC8420

Rev. B | Page 8 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CLSEL

16

CLR

15

LD

14

NC

13

CS

12

CLK

11

SDI

10

GND

9

NC = NO CONNECT

DAC8420

TOP VIEW

(Not to Scale)

Figure 4. PDIP and CERDIP

CLSEL

16

CLR

15

LD

14

NC

13

CS

12

CLK

11

SDI

10

GND

9

NC = NO CONNECT

DAC8420

TOP VIEW

(Not to Scale)

Figure 5. SOIC

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDD

Positive Power Supply, 5 V to 15 V.

4

VREFLO

Reference Input. Lower DAC ladder reference voltage input, equal to zero-scale output. Allowable

5

VREFHI

7, 6, 3, 2

VOUTA through VOUTD

Buffered DAC Analog Voltage Outputs.

8

VSS

Negative Power Supply, 0 V to −15 V.

9

GND

Power Supply, Digital Ground.

10

SDI

Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register,

which shifts data in, beginning with DAC Address Bit A1. This input is ignored when CS is high. SDI

is CMOS/TTL compatible. The format of the 16-bit serial word is shown in Table 8.

11

CLK

System Serial Data Clock Input, TTL/CMOS Levels. Data presented to the input SDI is shifted into

the internal serial-parallel input register on the rising edge of clock. This input is logically OR’ed

with CS.

12

CS

Control Input, Device Chip Select, Active Low. This input is logically OR’ed with the clock and

disables the serial data register input when high. When low, data input clocking is enabled (see

Table 6). CS is CMOS/TTL compatible.

13

NC

No Connect = Don’t Care.

14

LD

Control Input, Asynchronous DAC Register Load Control, Active Low. The data currently contained

in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD,

independent of CS. Input data must remain stable while LD is low. LD is CMOS/TTL compatible.

15

CLR

Control Input, Asynchronous Clear, Active Low. Sets internal data Register A through Register D to

zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is

unaffected by this control. CLR is CMOS/TTL compatible.

16

CLSEL

Control Input, Determines action of CLR. If high, a clear command sets the internal DAC Register A

through Register D to midscale (0x800). If low, the registers are set to zero (0x000). CLSEL is CMOS

/

TTL compatible.