Data Sheet

AD636

Rev. E | Page 11 of 16

slightly more restricted than in the dual supply connection. The

C2

3.3µF

AD636

ABSOLUTE

VALUE

SQUARER

DIVIDER

10kΩ

10kΩ

CURRENT

MIRROR

–

BUF

+

20kΩ

NONPOLARIZED

39kΩ

0.1µF

0.1µF

1kΩ TO 10kΩ

1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC

dB

BUF OUT

BUF IN

NC

NC

NC

COM

NC = NO CONNECT

+

–

Figure 11. Single-Supply Connection (See Text)

CHOOSING THE AVERAGING TIME CONSTANT

The AD636 computes the rms of both ac and dc signals. If the

input is a slowly varying dc voltage, the output of the AD636

tracks the input exactly. At higher frequencies, the average

output of the AD636 approaches the rms value of the input

signal. The actual output of the AD636 differs from the ideal

output by a dc (or average) error and some amount of ripple, as

demonstrated in Figure 12.

TIME

IDEAL

DOUBLE-FREQUENCY

RIPPLE

Figure 12. Typical Output Waveform for Sinusoidal Input

The dc error is dependent on the input signal frequency and the

frequency using the standard rms connection.

The ac component of the output signal is the ripple. There are

two ways to reduce the ripple. The first method involves using a

reduction in ripple. When measuring waveforms with high crest

factors (such as low duty cycle pulse trains), the averaging time

constant should be at least ten times the signal period. For example,

a 100 Hz pulse rate requires a 100 ms time constant, which

corresponds to a 4 μF capacitor (time constant = 25 ms per μF).

INPUT FREQUENCY (Hz)

100

0.01

1

10

0.1

1

10

100

0.1

0.01

*% dc ERROR + % RIPPLE (PEAK)

1

10

100

1k

10k

100k

1% SETTLING TIME FOR

STATED % OF READING

AVERAGING ERROR*

ACCURACY ±20% DUE TO

COMPONENT TOLERANCE

Figure 13. Error/Settling Time Graph for Use with the Standard RMS

Connection

is that the settling time for a step change in input level is

increased proportionately. Figure 13 shows the relationship

as for increasing signals (the values in Figure 13 are for decreasing

signals). Settling time also increases for low signal levels, as

shown in Figure 14.

rms INPUT LEVEL

10.0

7.5

0

10mV

100mV

1.0

5.0

2.5

1V

1mV

Figure 14. Settling Time vs. Input Level

A better method for reducing output ripple is the use of a post-

filter. Figure 15 shows a suggested circuit. If a single-pole filter

Figure 16, and the settling time is increased. For example, with

reduced from 10% of reading to approximately 0.3% of reading.

The settling time, however, is increased by approximately a

to permit faster settling times while still providing substantial

ripple reduction.