MCP47DA1 datasheet(52/76 Pages) MICROCHIP

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MCP47DA1

DS25118D-page 52

 2012-2013 Microchip Technology Inc.

8.1.1

DECREASING OUTPUT STEP SIZE

Due to the step voltage and output range of the

MCP47DA1, it may be desirable to reduce the step

voltage while also modifying the range of the output. A

common method to achieve this smaller step size is a

voltage divider on the DAC’s output. This allows the

VTRIP voltage to be lower than the minimum output volt-

age of the DAC (1/3 * VREF). Figure 8-2 illustrates this

concept. Equation 8-2 shows a quick estimation of the

wiper value given the desired voltage trip (VTRIP) point.

So, for example, if R1 = R2, then the VTRIP voltage

range is from 1/6 * VREF to 1/3 * VREF, where the VOUT

voltage range is from 1/3 * VREF to 2/3 * VREF. Also at

the VTRIP node, the step voltage is 1/2 the step voltage

at the VOUT node.

A bypass capacitor on the output of the voltage divider

plays a critical function in attenuating the output noise

of the DAC and the induced noise from the

environment.

FIGURE 8-2:

Example Circuit Of Set Point

or Threshold Calibration.

EQUATION 8-2:

VOUT AND VTRIP

ESTIMATIONS

8.1.2

BUILDING A “WINDOW” DAC

When calibrating a set point or threshold of a sensor,

typically only a small portion of the DAC output range is

utilized. If the LSb size is adequate enough to meet the

application’s accuracy needs, the unused range is

sacrificed without consequences. If greater accuracy is

needed, then the output range will need to be reduced

to increase the resolution around the desired threshold.

If the threshold is not near VREF, 2 • VREF, or VSS then

creating a “window” around the threshold has several

advantages. One simple method to create this “window”

is to use a voltage divider network with a pull-up and

pull-down resistor. Figure 8-3 and Figure 8-4 illustrate

this concept.

FIGURE 8-3:

Single-Supply “Window”

DAC.

EQUATION 8-3:

VOUT AND VTRIP

ESTIMATIONS

Note:

The VOUT voltage can also be scaled by a

resistor from the VREF pin to the system

reference voltage. Care should be taken

with this implementation due to the ± 20%

variation to the 30k

 typical resistance

from the VREF pin to ground (RVREF). This

variation in resistance directly effects the

actual VOUT voltage.

VCC+

VCC–

I2C™

2-wire

VREF

MCP47DA1

VDD

VOUT

Comp.

VTRIP

VSENSE

VOUT = (1/3) * VREF + (N * VS)

VS = VREF / 192

R1 + R2

VTRIP = VOUT *

VCC+

VCC–

I2C™

2-wire

VREF

MCP47DA1

VDD

VOUT

VCC+

VCC–

RSENSE

Comp.

VTRIP

VOUT = (1/3) * VREF + (N * VS)

VS = VREF / 192

VOUT * R23 + V23 * R1

R1 + R23

VTRIP =

R23

V23

VOUT

VTRIP

Thevenin

Equivalent

R2 * R3

R2 + R3

R23 =

(VCC+ * R2) * (VCC- * R3)

R2 + R3

V23 =

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