LPC4350_13 datasheet(2/153 Pages) NXP

2 / 153 page

LPC4350_30_20_10

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 26 March 2013

2 of 153

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

 On-chip memory

 Up to 264 kB SRAM for code and data use.

 Multiple SRAM blocks with separate bus access. Two SRAM blocks can be

powered down individually.

 64 kB ROM containing boot code and on-chip software drivers.

 128 bit general-purpose One-Time Programmable (OTP) memory.

 Clock generation unit

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature and

voltage.

 Ultra-low power Real-Time Clock (RTC) crystal oscillator.

 Three PLLs allow CPU operation up to the maximum CPU rate without the need for

a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the

third PLL can be used as audio PLL.

 Clock output.

 Configurable digital peripherals

 Serial GPIO (SGPIO) interface.

 State Configurable Timer (SCT) subsystem on AHB.

 Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and

outputs to event driven peripherals like the timers, SCT, and ADC0/1.

 Serial interfaces

 Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to

52 MB per second.

 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time

stamping (IEEE 1588-2008 v2).

 One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip high-speed PHY (USB0).

 One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY (USB1).

 USB interface electrical test software included in ROM USB stack.

 Four 550 UARTs with DMA support: one UART with full modem interface; one

UART with IrDA interface; three USARTs support UART synchronous mode and a

smart card interface conforming to ISO7816 specification.

 Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller

excludes operation of all other peripherals connected to the same bus bridge See

Figure 1 and Ref. 1.

 Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

 One SPI controller.

 One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I2C-bus specification. Supports data rates of up to

1Mbit/s.

 One standard I2C-bus interface with monitor mode and with standard I/O pins.

 Two I2S interfaces, each with DMA support and with one input and one output.

LPC4350 датащи(PDF) 2 Page - NXP Semiconductors

LPC4350 датащи(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL