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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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JS28F128P33TF70A датащи(PDF) 18 Page - Microchip Technology |
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JS28F128P33TF70A датащи(HTML) 18 Page - Microchip Technology |
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18 / 88 page  P33-65nm Datasheet Jul 2011 18 Order Number: 208034-04 6.2 Device Command Bus Cycles Device operations are initiated by writing specific device commands to the CUI. See Table 6, “Command Bus Cycles” on page 18. Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to the CUI initiates a sequence of internally-timed functions that culminate in the completion of the requested task. However, the operation can be aborted by either asserting RST# or by issuing an appropriate suspend command. Configuration 0x60 Read Configuration Register Setup First cycle of a 2-cycle command; prepares the CUI for device read configuration. If the Set Read Configuration Register command (0x03) is not the next command, the CUI sets Status Register bits SR.5 and SR.4, indicating a command sequence error. 0x03 Read Configuration Register If the previous command was Read Configuration Register Setup (0x60), the CUI latches the address and writes A[16:1]to the Read Configuration Register. Following a Configure RCR command, subsequent read operations access array data. blank check 0xBC Blank Check First cycle of a 2-cycle command; initiates the Blank Check operation on a main block. 0xD0 Blank Check Confirm Second cycle of blank check command sequence; it latches the block address and executes blank check on the main array block. other 0xEB Extended Function Interface This command is used in extended function interface. first cycle of a multiple- cycle command second cycle is a Sub-Op-Code, the data written on third cycle is one less than the word count; the allowable value on this cycle are 0 through 511. The subsequent cycles load data words into the program buffer at a specified address until word count is achieved. Table 5: Command Codes and Definitions (Sheet 3 of 3) Mode Code Device Mode Description Table 6: Command Bus Cycles (Sheet 1 of 2) Mode Command Bus Cycles First Bus Cycle Second Bus Cycle Oper Addr(1) Data(2) Oper Addr(1) Data(2) Read Read Array 1 Write DnA 0xFF - - - Read Device Identifier ≥ 2Write DnA 0x90 Read DBA + IA ID Read CFI ≥ 2Write DnA 0x98 Read DBA + CFI-A CFI-D Read Status Register 2 Write DnA 0x70 Read DnA SRD Clear Status Register 1 Write DnA 0x50 - - - Program Word Program 2 Write WA 0x40 Write WA WD Buffered Program(3) > 2 Write WA 0xE8 Write WA N - 1 Buffered Enhanced Factory Program (BEFP)(4) > 2 Write WA 0x80 Write WA 0xD0 Erase Block Erase 2 Write BA 0x20 Write BA 0xD0 Suspend Program/Erase Suspend 1Write DnA 0xB0 - - - Program/Erase Resume 1Write DnA 0xD0- - - |
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