WM8953ECSSLASHRV datasheet(79/100 Pages) WOLFSON

79 / 100 page

Production Data

WM8953

PD, January 2009, Rev 4.0

POWER MANAGEMENT

POWER MANAGEMENT REGISTERS

The WM8953 has two control registers that allow users to select which functions are active. For

minimum power consumption, unused functions should be disabled. To minimise pop or click noise,

it is important to enable or disable functions in the correct order.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

MICBIAS_ENA

(rw)

MICBIAS Enable

0 = OFF (high impedance output)

1 = ON

2:1

VMID_MODE

[1:0]

(rw)

00b

Vmid Divider Enable and Select

00 = Vmid disabled (for OFF mode)

01 = 2 x 50k

Ω divider (Normal mode)

10 = 2 x 250k

Ω divider (Standby mode)

11 = 2 x 5k

Ω divider (for fast start-up)

R1 (1h)

VREF_ENA

(rw)

VREF Enable (Bias for all analogue

functions)

0 = VREF bias disabled

1 = VREF bias enabled

PLL_ENA

(rw)

PLL Enable

0 = disabled

1 = enabled

TSHUT_ENA

(rw)

Thermal Sensor Enable

0 = Thermal sensor disabled

1 = Thermal sensor enabled

OPCLK_ENA

(rw)

GPIO Clock Output Enable

0 = disabled

1 = enabled

AINL_ENA

(rw)

Left Input Path Enable

0 = disabled

1 = enabled

AINR_ENA

(rw)

Left Input Path Enable

0 = disabled

1 = enabled

LIN34_ENA

(rw)

LIN34 Input PGA Enable

0 = disabled

1 = enabled

LIN12_ENA

(rw)

LIN12 Input PGA Enable

0 = disabled

1 = enabled

RIN34_ENA

(rw)

RIN34 Input PGA Enable

0 = disabled

1 = enabled

RIN12_ENA

(rw)

RIN12 Input PGA Enable

0 = disabled

1 = enabled

ADCL_ENA

(rw)

Left ADC Enable

0 = disabled

1 = enabled

R2 (02h)

ADCR_ENA

(rw)

Right ADC Enable

0 = disabled

1 = enabled

Table 51 Power Management

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