AD7658BSTZ datasheet(24/32 Pages) AD

24 / 32 page

AD7656/AD7657/AD7658

Data Sheet

Rev. D | Page 24 of 32

Software Selection of ADCs

The H/S SEL pin determines the source of the combination of

ADCs that are to be simultaneously sampled. When the H/S SEL

pin is logic low, the combination of channels to be simultaneously

sampled is determined by the CONVST A, CONVST B, and

CONVST C pins. When the H/S SEL pin is logic high, the

combination of channels selected for simultaneous sampling is

determined by the contents of the Control Register DB15 to

Control Register DB13. In this mode, a write to the control

The control register is an 8-bit write-only register. Data is written

to this register using the CS and WR pins and the DB[15:8] data

pins (see Figure 29). The control register is shown in Table 10.

To select an ADC pair to be simultaneously sampled, set the

corresponding data line high during the write operation.

The AD7656/AD7657/AD7658 control register allows

individual ranges to be programmed on each ADC pair.

DB12 to DB10 in the control register are used to program

the range on each ADC pair.

After a reset occurs on the AD7656/AD7657/AD7658, the

control register contains all zeros.

The CONVST A signal is used to initiate a simultaneous

conversion on the combination of channels selected via the

control register. The CONVST B and CONVST C signals can

be tied low when operating in software mode (H/S SEL = 1).

The number of read pulses required depends on the number

of ADCs selected in the control register and on whether the

devices are operating in word or byte mode. The conversion

results are output in ascending order.

During the write operation, Data Bus Bit DB15 to Bit DB8 are

bidirectional and become inputs to the control register when

RD is logic high and CS and WR are logic low. The logic state

on DB15 through DB8 is latched into the control register when

WR goes logic high.

Table 10. Control Register Bit Function Descriptions

(Default All 0s)

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

RNGC

RNGB

RNGA

REFEN

REFBUF

Table 11.

Bit

Mnemonic

Comment

DB15

This bit is used to select Analog Inputs V5

and V6 for the next conversion.

When this bit = 1, V5 and V6 are

simultaneously converted on the

next CONVST A rising edge.

DB14

This bit is used to select Analog Inputs

V3 and V4 for the next conversion.

When this bit = 1, V3 and V4 are

simultaneously converted on the

next CONVST A rising edge.

DB13

This bit is used to select Analog Inputs

V1 and V2 for the next conversion.

When this bit = 1, V1 and V2 are

simultaneously converted on the

next CONVST A rising edge.

DB12

RNGC

This bit is used to select the analog input

range for Analog Inputs V5 and V6.

When this bit = 1, the ±2 × VREF mode is