AD7658BSTZ datasheet(22/32 Pages) AD

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AD7656/AD7657/AD7658

Data Sheet

Rev. D | Page 22 of 32

100nF

DVCC

100nF

DVCC

AVCC

AGND

DGND

VDRIVE DGND

VDD

AGND

100nF

VSS

AGND

100nF

REFCAPA, B, C

AGND

REFIN/OUT

AGND

D0 TO D15

CONVST A, B, C

BUSY

SER/PAR

H/S

W/B

RANGE

RESET

STBY

VDRIVE

AD7656/AD7657/AD7658

10µF

µP/µC/DSP

10µF

DIGITAL SUPPLY

VOLTAGE +3V OR +5V

ANA L OG SUPPLY

VOLTAGE 5V1

1DECOUPLING SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN.

2SEE POWER SUPPLY CONFIGURATION SECTION.

+9.5V TO +16.5V2

SUPPLY

2.5V

REF

SIX ANALOG

INPUTS

–9.5V TO –16.5V2

SUPPLY

PARALLEL

INTERFACE

Figure 26. Typical Connection Diagram

The VDRIVE supply is connected to the same supply as the

processor. The voltage on VDRIVE controls the voltage value

of the output logic signals.

The VDD and VSS signals should be decoupled with a minimum

10 µF decoupling capacitor. These supplies are used for the high

voltage analog input structures on the AD7656/AD7657/AD7658

analog inputs.

DRIVING THE ANALOG INPUTS

Together, the driver amplifier and the analog input circuit used

for the AD7656 must settle for a full-scale step input to a 16-bit

level (0.0015%), which is within the specified 550 ns acquisition

time of the AD7656. The noise generated by the driver amplifier

needs to be kept as low as possible to preserve the SNR and

transition noise performance of the AD7656.

The driver also needs to have a THD performance suitable to

that of the AD7656. The AD8021 meets all these requirements.

The AD8021 needs an external compensation capacitor of

10 pF. If a dual version of the AD8021 is required, the AD8022

can be used. The AD8610 and the AD797 can also be used to

drive the AD7656/AD7657/AD7658.

INTERFACE SECTION

The AD7656/AD7657/AD7658 provide two interface options, a

parallel interface and a high speed serial interface. The required

interface mode is selected via the SER/PAR pin. The parallel

interface can operate in word (W/B = 0) or byte (W/B = 1) mode.

The interface modes are discussed in the following sections.

Parallel Interface (SER/PAR = 0)

The AD7656/AD7657/AD7658 consist of six 16-/14-/12-bit

ADCs, respectively. A simultaneous sample of all six ADCs can

be performed by connecting all three CONVST pins together,

CONVST A, CONVST B, and CONVST C. The AD7656/AD7657/

AD7658 need to see a CONVST pulse to initiate a conversion;

this should consist of a falling CONVST edge followed by a

rising CONVST edge. The rising edge of CONVSTx initiates

simultaneous conversions on the selected ADCs. The AD7656/

AD7657/AD7658 contain an on-chip oscillator that is used to

perform the conversions. The conversion time, tCONV, is 3 µs.

The BUSY signal goes low to indicate the end of conversion.

The falling edge of the BUSY signal is used to place the track-

and-hold into track mode. The AD7656/AD7657/AD7658 also

allow the six ADCs to be converted simultaneously in pairs by

pulsing the three CONVST pins independently. CONVST A is

used to initiate simultaneous conversions on V1 and V2,

CONVST B is used to initiate simultaneous conversions on

V3 and V4, and CONVST C is used to initiate simultaneous

conversions on V5 and V6. The conversion results from the

simultaneously sampled ADCs are stored in the output data

registers.

Data can be read from the AD7656/AD7657/AD7658 via the

parallel data bus with standard CS and RD signals (W/B = 0).

To read the data over the parallel bus, SER/PAR should be tied

low. The CS and RD input signals are internally gated to enable

the conversion result onto the data bus. The data lines DB0 to

DB15 leave their high impedance state when both CS and RD

are logic low.

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