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PCAL9554B датащи(PDF) 18 Page - NXP Semiconductors

номер детали PCAL9554B
подробное описание детали  Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up and Agile I/O
PDF  42 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCAL9554B датащи(HTML) 18 Page - NXP Semiconductors

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PCAL9554B_PCAL9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 December 2012
18 of 42
NXP Semiconductors
PCAL9554B; PCAL9554C
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
8.4 Power-on reset requirements
In the event of a glitch or data corruption, PCAL9554B/PCAL9554C can be reset to its
default conditions by using the power-on reset feature. Power-on reset requires that the
device go through a power cycle to be completely reset. This reset also happens when the
device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 17 and Figure 18.
Table 18 specifies the performance of the power-on reset feature for
PCAL9554B/PCAL9554C for both types of power-on reset.
Fig 17. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD
Fig 18. VDD is lowered below the POR threshold, then ramped back up to VDD
002aah329
VDD
time
ramp-up
ramp-down
(dV/dt)r
(dV/dt)f
re-ramp-up
(dV/dt)r
time to re-ramp
when VDD drops
below 0.2 V or to VSS
td(rst)
002aah330
VDD
time
ramp-down
(dV/dt)f
ramp-up
(dV/dt)r
time to re-ramp
when VDD drops
to VPOR(min) − 50 mV
td(rst)
VI drops below POR levels



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