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TMPR28051 датащи(PDF) 68 Page - Agere Systems

номер детали TMPR28051
подробное описание детали  TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
PDF  90 Pages
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TMPR28051 датащи(HTML) 68 Page - Agere Systems

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Data Sheet
TMPR28051 STS-1/AU-3 (STM-0) Mapper
August 1999
54
Lucent Technologies Inc.
Microprocessor Interface Description (continued)
Register Architecture Description (continued)
Digital Jitter Attenuator Controls (0x8A—0x8F)
Table 24. Registers 0x8A—0x8F: Digital Jitter Attenuator Controls
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x8A—0x8F
—
—
The bits in registers 0x8A—0x8F are used to control vari-
ous aspects of the digital jitter attenuator. Two programma-
ble terms are used to set the 2nd order loop damping factor
and natural frequency of the PLL. These terms are the gain
threshold, set by DJAGTHR-[23:0] in registers
0x8D—0x8F, and scale value, set by DJASCALE-[15:0] in
registers 0x8B—0x8C. The PLL bandwidth can be set,
using the above registers, to accommodate various system
constraints.
See
below.
0x8A
7—0
SCALETHR-[7:0] Scale Threshold.
0xFF
0x8B
7—0
DJASCALE-[15:8] Scale Value.
0x0F
0x8C
7—0
DJASCALE-[7:0]
0xCA
0x8D
7—0
DJAGTHR-[23:16]
Gain Threshold.
0x00
0x8E
7—0
DJAGTHR-[15:8]
0xFE
0x8F
7—0
DJAGTHR-[7:0]
0x50



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