TMPR28051 datasheet(30/90 Pages) AGERE

30 / 90 page

Data Sheet

TMPR28051 STS-1/AU-3 (STM-0) Mapper

August 1999

Lucent Technologies Inc.

DS1/E1 to STS-1 Block Descriptions

(continued)

SPE Insertion Logic (continued)

The device can transmit the data as either a serial bit

stream (TXSERIAL = 1 in register 0x02, bit 6) or as a

parallel byte of data (TXSERIAL = 0 in register 0x02,

bit 6). There are two parallel modes of operation: bus

mode and nonbus mode. Bus mode allows multiple

TMPR28051 devices to operate on a 19.44 MHz bus;

in nonbus mode, the device transmits data in a

point-to-point fashion at 6.48 MHz. In either parallel

mode, the device sends a parity bit with the data.

This parity bit is configurable to be either odd

(TXPARITY = 1 in register 0x02, bit position 4) or even

(TXPARITY = 0 in register 0x02, bit position 4) parity.

The bus mode of operation requires the device to

select which STS-1 time slot of the three that are avail-

able to transmit data. The TBUSMODE bit (bit 2) in reg-

ister 0x12 determines whether the device operates in

bus mode (TBUSMODE = 1) or nonbus mode

(TBUSMODE = 0). By default, the device powers up in

bus mode. The TBUSPOS bits (bit 1 and bit 0) in regis-

ter 0x12 determine in which of the three time slots the

device transmits. By default, the device does not trans-

mit (TBUSPOS-[1:0] = 00 in register 0x12), but it can

be configured to transmit during any of the three STS-1

time slots on the 19.44 MHz bus.

In all three modes, the device frame sync input allows

the 8 kHz STS-1 frames as well as the 2 kHz VT super-

frames to be aligned.

STS-1 to DS1/E1 Block Descriptions

Loopback Select Logic

The device can be configured to loop back the transmit

STS-1 (STS1LB = 1 in bit 0 of register 0x01) or accept

the receive STS-1 signal (STS1LB = 0 in bit 0 of regis-

ter 0x01). When the receive STS-1 signal is selected,

the user can configure which edge of the clock to use

to retime the data (RXSTS1EDGE = 1 in bit 3 of regis-

ter 0x02 uses the rising edge; RXSTS1EDGE = 0 in

bit 3 of register 0x02 uses the falling edge).

SPE Locate

The device can receive data as either a serial bit

stream (RXSERIAL = 1 in bit 7 of register 0x02) or as a

parallel byte (RXSERIAL = 0 in bit 7 of register 0x02).

In the parallel mode, the device receives a parity bit

with the data. This bit is configurable to odd

(RXPARITY = 1 in bit 5 of register 0x02) or even

(RXPARITY = 0 in bit 5 of register 0x02) parity. Errors

in this bit are reported to the microprocessor

(RXPARER in bit 6 of register 0x03).

The bus mode of operation is similar to normal opera-

tion in the DS1/E1 to STS-1 direction. The device

defaults to the bus mode (RBUSMODE = 1 in bit 5 of

receive channels (RBUSPOS-[1:0] = 00 in bit 4 and

bit 3 of register 0x12). The sync pulse is used only to

define time slot #1 of the three that are possible. Bus

mode operation requires at least one sync pulse to

define the time slot.

The STS-1 locate block performs the functions neces-

sary to locate the SPE. The device will frame on the

incoming STS-1 signal, and indicate when it is in the

out of frame (OOF) condition (STS1OOF = 1 in bit 0 of

(STS1LOF = 1 in bit 1 of register 0x03). Loss of frame

is defined as being in the OOF condition for 3 ms or

more. Both the OOF and LOF are current state condi-

tions; they hold their value for a minimum of 500

µs

after the event. The indications reset if the condition is

no longer true.

The device monitors the received data bytes for contin-

uous ones or zeros. If the number of continuous data

bytes exceeds the provisioned value (LOSDET-[7:0] in

bit 0 of register 0x05) is declared. If the value in

LOSDET-[7:0] in register 0x91 is 0x00, then LOS is not

declared.

STS-1/AU-3 Terminate

The STS-1 terminate block can descramble the output

data (STS1DSCR = 1 in bit 1 of register 0x01) or output

the received data without descrambling

(STS1DSCR = 0 in bit 1 of register 0x01). It is useful to

turn off descrambling if the data is received locally from

a higher-rate signal where descrambling has already

taken place.

For performance monitoring purposes, there are a

number of BIP and REI error counters (registers

0xC0—0xFF) in the receive section of the device. All of

these internal counters are comprised of a running

error counter and a hold register that presents stable

results to the microprocessor. The counts in all of the

running counters are latched to the hold registers when

LATCH_CNT (bit 3) in register 0x00 is written from 0 to

1. This also resets all of the running counters. The

results are then held until read by the microprocessor.

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