OR3C55 datasheet(75/210 Pages) AGERE

75 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Programmable Clock Manager (PCM)

(continued)

Delay-Locked Loop (DLL) Mode

DLL mode is used for implementing a delayed clock

(phase adjustment), clock doubling, and duty cycle

adjustment. All DLL functions stem from a delay line

with 32 taps. The delayed input clock is pulled from var-

ious taps and processed to implement the desired

result. There is no feedback clock in DLL mode, provid-

ing a very stable output and a fast lock time for the out-

put clock.

DLL mode is selected by setting bit 0 in PCM register

five to a 0. The settings for the various submodes of

DLL mode are described in the following paragraphs.

Divider DIV0 may be used with any of the DLL modes

to divide the input clock by an integer factor of 1 to 8

prior to implementation of the DLL process.

Delayed Clock

A delayed version of the input clock can be constructed

in DLL mode. The output clock can be delayed by

increments of 1/32 of the input clock period. Express

CLK and system CLK outputs in delay modes are

selected by setting register six, bits [5:4] to 10 or 11 for

ExpressCLK

output, and/or bits [7:6] to 10 for system

clock output. The delay value is entered in register four.

See register four programming details for more infor-

mation. Delay values are also shown in the second col-

umn of Table 27.

Note that when register six, bits [5:4] are set to 11, the

ExpressCLK

output is divided by an integer factor from

1 to 8 while the system clock cannot be divided. The

ExpressCLK

divider is provided so that the I/O clocking

provided by the ExpressCLK can operate slower than

the internal system clock. This allows for very fast inter-

nal processing while maintaining slower interface

speeds off-chip for improved noise and power perfor-

mance or to interoperate with slower devices in the sys-

tem. The divisor of the ExpressCLK frequency is

selected in register two. See the register two program-

ming details for more information.

1x Clock Duty-Cycle Adjustment

A duty-cycle adjusted replica of the input clock can be

constructed in DLL mode. The duty cycle can be

adjusted in 1/32 (3.125%) increments of the input clock

period. DLL 1x clock mode is selected by setting bit 4

of register five to a 1, and output clock source selection

is selected by setting register six, bits [5:4] to 01 for

ExpressCLK

output, and/or bits [7:6] to 01 for system

clock output. The duty-cycle percentage value is

entered in register four. See register four programming

details for more information. Duty cycle values are also

shown in the third column of Table 27.

Table 27. DLL Mode Delay/1x Duty Cycle

Programming Values

7 6 5 4 3 2 1 0

Delay

(CLK_IN/32)

Duty Cycle

(% of CLK_IN)

0 0 X X X 0 0 0

3.125

0 0 X X X 0 0 1

6.250

0 0 X X X 0 1 0

9.375

0 0 X X X 0 1 1

12.500

0 0 X X X 1 0 0

15.625

0 0 X X X 1 0 1

18.750

0 0 X X X 1 1 0

21.875

0 0 X X X 1 1 1

25.000

0 1 X X X 0 0 0

28.125

0 1 X X X 0 0 1

31.250

0 1 X X X 0 1 0

34.375

0 1 X X X 0 1 1

37.500

0 1 X X X 1 0 0

40.625

0 1 X X X 1 0 1

43.750

0 1 X X X 1 1 0

46.875

0 1 1 1 1 X X X

50.000

1 0 0 0 0 X X X

53.125

1 0 0 0 1 X X X

56.250

1 0 0 1 0 X X X

59.375

1 0 0 1 1 X X X

62.500

1 0 1 0 0 X X X

65.625

1 0 1 0 1 X X X

68.750

1 0 1 1 0 X X X

71.875

1 0 1 1 1 X X X

75.000

1 1 0 0 0 X X X

78.125

1 1 0 0 1 X X X

81.250

1 1 0 1 0 X X X

84.375

1 1 0 1 1 X X X

87.500

1 1 1 0 0 X X X

90.625

1 1 1 0 1 X X X

93.750

1 1 1 1 0 X X X

96.875

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