P17/29

Rev. M, May 2010

ML5012

The CE input pin is an input for chip enabled controlled and chip reset controlled. When CE=0, the chip will enter

reset condition. In this time, all functions stops operating and the DOUT pin becomes tri-state output, and PADEOC

becomes low output. For reducing the power consumption, it is recommended to reset CE pin as 0 when ADC

function is inactive.

When CE=1, the chip will wake up from reset condition. All functions have ready to operate and the DOUT pin

becomes output data. The chip will get into waiting state to receive the command from serial interface.

Since no power on reset circuitry is built in this chip, it is necessary to set CE pin to 0 after power on state to initiate

this chip.

3. PGA OFFSET Initialization

After system power up, ML5012 will initialize the PGA Offset register automatically.

The AD_Clock controls the AD conversion clock frequency; slower clock can save power, but longer conversion time.

The STA_OPT, is the startup time option, the shorter the startup time, the sooner will get the result, but the AD result

may not be stable.

SMODE is the successive AD conversion mode, when enabled, the ADC will not be automatically disabled after each

AD conversion, otherwise, the ADC will be disabled after each AD conversion to save power, when enabled, and the

STA_OPT will not have effect after the first conversion, as the ADC is always enabled.

VGND_EN, “VREF = AGND” and VMID_EN, “VREF = (VR-AGND)/2” are selecting the VREF voltage to the PGA, from

the below output voltage equation of the PGA.

VREF

GAIN

PGA

V

V

OUT

PGA

CHB

CHA

+

×

−

=

_

)

(

_

Then the PGA_OUT will input to the ADC directly.