P23/29

Rev. M, May 2010

ML5012

The comparison mode compares the level of analog voltage coming from channel AB and B with internal voltage set

by the A/D configuration register, storing the result into the bit RSLT of A/D configuration register.

The time required for the converter to complete conversion is as follows:

Conversion duration = Oscillator clock period x 15

Example:

(a). 150us (oscillator clock at 100KHz)

(b). 75us (oscillator clock at 200kHz)

6-1. Selecting PGA channel AB & B input pin, PGA Gain & A/D enable control

Executing STCH command to enable Oscillator and then select one of PGA input channel AB & B for

differential analog input or single end input.

Setting of Oscillator enable pins

Before using A/D conversion, ENOSC bit must be set to 1 to start-up the oscillator in order to

provide the clock for A/D conversion mode.

It is recommended to turn off the oscillator when A/D conversion mode is completed in order to

reduce the power consumption.

Setting of AD Output Range

Setting of AD Output Range

Output Range

AD_Range = 0

0 ~ 4,095

AD_Range = 1

-2,047 ~ 2,047

Please refer to Section 4-2 for more details.