CC3000MOD

SWRS126 – NOVEMBER 2012

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Table 4 lists the SPI timing parameters.

Table 4. SPI Timing Parameters

Symbol

Min

Max

Unit

Clock period

62.5

ns

High pulse width

(including jitter and duty

ns

cycle)

RX setup time; minimum

time in which data is

5

ns

stable before capture

edge

RX hold time; minimum

time in which data is

5

stable after capture edge

TX setup propagation

time; maximum time from

10.2

launch edge until data is

stable

TX hold propagation time;

minimum time of data

3

stable after launch edge

Capacitive load on

20

pF

interface

(1)

The SPI_CS signal is considered to be asynchronous.

(2)

In this example, launch is on the rising edge, and capture is on the falling edge. The opposite scheme can be configured.

(3)

40% to 60% DC (valid for the minimum clock period)

8

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