ADSP2181 datasheet(15/32 Pages) AD

номер детали	ADSP2181

подробное описание детали	DSP Microcomputer

PDF	32 Pages

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производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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15 / 32 page

ADSP-2181

–15–

REV. D

Parameter

Min

Max

Unit

Interrupts and Flag

Timing Requirements:

tIFS

IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4

0.25tCK + 15

tIFH

IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4

0.25tCK

Switching Characteristics:

tFOH

Flag Output Hold after CLKOUT Low

0.5tCK – 7

tFOD

Flag Output Delay from CLKOUT Low

0.5tCK + 5

NOTES

1If

IRQx and FI inputs meet t

IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)

2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

5Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.

tFOD

tFOH

tIFH

tIFS

CLKOUT

FLAG

OUTPUTS

IRQx

PFx

Figure 9. Interrupts and Flags

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