REV. 0

ADP3422

–13–

This ensures that the output voltage does not bounce back tempo-

rarily right after a load transient, i.e., the output impedance of

the converter is purely resistive. The bounce-back is undesirable

because it increases the peak-to-peak deviation in the output

voltage. From (3), the optimal capacitance value is:

C

CR

RR

OC

OE

CD

=

(11)

the calculated one as possible. It is generally recommended to

two equations.

The output impedance is now set.

The next step in the design is to determine the value of the

inductor side and is determined by:

R

IR

V

t

R

L

I

A

RPP

CS

IM D OFF

CS

H

=

–

/

()

2

(12)

including delays through the ADP3422, ADP3415, and the

by a resistor on the ADP3422’s HYSSET pin, which sets the

current that is hysteretically switched in and out of the RAMP

pin. Assuming a turn-off delay of 50 ns and a hysteresis-setting

current of 30

To protect the converter, the hysteretic current limiting should

connects between the CS– pin and the core output is given by:

R

kR

I

I

I

CL

I

CS

O MAX

RPP

H

=

+

(/ )

()

2

3

(13)

limit point 15% above the maximum rated core current. Using

the preceding design target values, a value of 441

Ω for R

calculated.

In order to optimize the power savings by always using the

minimum allowed CPU supply voltage, the IMVP-2 specifica-

tion introduces two operating-mode-dependent voltage shifts.

The first shift is for optimizing the output voltage when the

battery-optimized-mode (BOM) VID code is selected. The

the BSHIFT pin and ground. The shift will be used whenever

the

BOM pin is driven low, indicating that the BOM VID

code is selected. The shift is given by:

V

R

R

V

R

R

BSHIFT

A

BSHIFT

VID BOM

D

C

=+













–

,

1

(14)

The second shift is for optimizing the output voltage when the

Deep Sleep operating mode is selected in conjunction with

either the POM or BOM VID codes. This shift is achieved by

ground. The shift will be used whenever the

DPSLP pin is

driven low. The shift is given by:

V

R

R

V

R

R

DSHIFT

A

DSHIFT

VID BOM

D

C

=+













–

,

1

(15)

PRINTED CIRCUIT BOARD LAYOUT

CONSIDERATIONS

The following guidelines are recommended for optimal perfor-

mance of the ADP3422 and ADP3415 in a power converter.

The circuitry is considered in three parts: the power switching

circuitry, the output filter, and the control circuitry.

Placement Overview

1. For ideal component placement, the output filter capacitors

will divide the power switching circuitry from the control

section. As an approximate guideline, considered on a

single-sided PCB, the best layout would have components

aligned in the following order: ADP3415, MOSFETs and

input capacitor, output inductor, current sense resistor, output

capacitors, control components and ADP3422. Note that

the ADP3422 and ADP3415 are completely separated for

an ideal layout, which is only possible with a two-chip solution.

This will minimize jitter in the control caused by having the

driver and MOSFETs close to the control and give more

freedom in the layout of the power switching circuitry.

2. Whenever a power dissipating component (e.g., a power

MOSFET) is soldered to a PCB, the liberal use of vias, both

directly on the mounting pad and immediately surrounding

it, is recommended. Two important reasons for this are:

improved current rating through the vias (if it is a current

path), and improved thermal performance—especially if

the vias extend to the opposite side of the PCB where a

plane can more readily transfer heat to air.

Power Switching Circuitry

ADP3415, MOSFETs, and Input Capacitors

3. Locate the ADP3415 near the MOSFETs so the parasitic

inductance in the gate drive traces and the trace to the SW

pin is small, and so that the ground pins of the ADP3415

are closely connected to the lower MOSFET’s source.

4. Locate at least one substantial (i.e., > ~10

µF) input bypass

MLC capacitor close to the MOSFETs so that the physical

area of the loop enclosed in the electrical path through the

bypass capacitor and around through the top and bottom

MOSFETs (drain-source) is small. This is the switching

power path loop.

5. Make provisions for thermal management of all the

MOSFETs. Heavy copper and wide traces to ground and

power planes will help to pull the heat out. Heat sinking

by a metal tap soldered in the power plane near the

MOSFETs will help. Even just small airflow can help

tremendously. Paralleled MOSFETs will help spread the

heat, even if the on-resistance is higher.