REV. 0

ADP3422

–12–

Application Schematic

Figure 3 shows the simplified application schematic of the

ADP3422 control IC. The ADP3422, together with its com-

panion dual MOSFET driver IC, the ADP3415, controls a

hysteretic converter that generates the core voltage for the CPU.

Design Procedure—Power Stage Components

The first step of the converter design is to select the MOSFETs

to be used based on acceptable dc and switching losses. For this

selection, the designer is referred to the MOSFET manufac-

turers who may provide not only a recommendation for the

MOSFETs to be used for the specific application, but also

data and/or guidelines for determining an acceptable maxi-

mum operating frequency.

With this information, the next step is to choose an inductance

value—usually the smallest available value, that will yield an

acceptable ripple current. A ripple current 30%~60% of the

maximum core current is recommended. Inductance, frequency,

and ripple current are related by formula (6), derived from (5):

L

fI

VV

V

V

MAX

RPP

IM

VID

VID

IM

=

1(

–

)

(6)

where:

L = inductance value

A standard value of 660 nH is available.

restrictions are that (1) the resistance should not be higher than

the core converter output impedance defined by Intel’s IMVP-2

specification, and (2) the resistance should not be so low that

the errors in reading the current sense signal become a problem.

The IMVP-2 specification requires that the converter output

of the nominal output impedance provides sufficient protection

against errors in the current sense signal. The chosen value is

Ω.

that a properly sized resistor is selected:

PR

I

CS

CS

O MAX

=

()

2

(7)

sense resistor is 542 mW.

The final step in finishing the design of the power stage is select-

ing the output capacitors. There are two primary considerations

in choosing those capacitors. The total ESR may not exceed the

output resistance required by Intel’s IMVP-2 specification. Also

the total capacitance must be checked to make sure that it is

sufficient to prevent overshoot beyond the voltage step caused

by the ESR during a full load transient, according to the formula:

C

LI

I

RV

OMIN

O MAX

O MIN

OUT

L

()

()

(

)

(

–

)

=

×

×

(8)

the voltage applied across the inductor in order to ramp the

current in the direction of the load step. The minimum CPU

voltage represents a critical performance limit that must not be

violated during a load step increase. Therefore, the minimum

capacitance must never be less than the calculated value when

inductor to ramp up the current. However, overshoot would still

occur unless the capacitance is greater than the calculated value

given by:

V

L

C

I

I

IV

R

I

V

OS

O

O MAX

RPP

O MIN

VID

OUT O MAX

VID

=+

























+

[]

()

(

)

()

––

–

2

2

22

(9)

For this design example, output capacitors with a capacitance

of 150

µF and a maximum ESR of 20 mΩ are chosen. Given

Ω, five capacitors would be needed to

achieve a total ESR of not more than 4 m

Ω. The total capaci-

tance of five of these capacitors is 750

µF. This capacitance is

greater than the value required for a load step increase, even

for an input voltage as low as 6 V; but it is less than what is

needed to prevent an overshoot for a load step decrease, where

only the output voltage is applied across the inductor to ramp

down the current to the minimum value. Assuming that the

Design Procedure—Control Circuit Components

The output resistance is implemented by using the proper ratio

of two resistors, which connect to the REG pin. One resistor,

to the core voltage. From (2):

R

R

RR

R

R

D

C

ET

CS

CS

=

––

(10)

resistor and the CPU measurement point.

There is no inherent restriction on the absolute value of either

Ω range are recommended.

These resistors can now be selected.