ADMC300BST datasheet(15/42 Pages) AD

15 / 42 page

ADMC300

–15–

REV. B

effectively subdivided into 128 equal time slices. The value

written to the ADCSYNC register is the number of such time

slices before the PWMSYNC pulse that the CONVST pulse is

active. In other words, the occurrence of the CONVST pulse

lags the PWMSYNC pulse of Figure 9 (b) by a time, T

OFFSET,

that can be expressed as a fraction of the ADC update period:

TOFFSET

(128

− ADCSYNC)

128

ADCDIVn

f CLKIN









Therefore, for the case where ADCDIVA is 0x180 and ADCSYNC

is 0x060, the CONVST pulse will lag the PWMSYNC pulse by a

quarter of the ADC update period, or 7.68

µs, with a 12.5 MHz

CLKIN. The ability to phase shift the ADC update relative to

the PWMSYNC pulse is available only in single update mode of

the PWM.

It is also possible to operate the ADCs at a faster update rate

than the PWM switching frequency and still maintain synchro-

nism, as illustrated in Figure 9 (c). In this example, the value

written to the ADCDIV registers is three times larger than the

value written to the PWMTM register, so that the ADC update

rate is three times faster than the PWM switching frequency.

Synchronism is maintained by setting Bits 7 and 8 of the

ADCCTRL register. In addition, it is possible to introduce a

phase shift between the ADC update and PWMSYNC pulses

while operating at different frequencies, as illustrated by Figure 9

(d). The offset is defined by the ADCSYNC register as a fraction

of the ADC update period in an identical manner to before.

ADC Transfer Characteristics

Each ADC converter of the ADMC300 consists of an input

modulator stage and a decimation filter stage that produces the

final conversion result. The output of the decimation filters are

16-bit, left-aligned, two’s complement representation of the

input signal, VIN. The ideal ADC transfer characteristics for

both single-ended and differential modes are shown in Figure

10. The transfer characteristics of the ADC when operated in

the differential configuration are shown in Figure 10 (a) and for

the single-ended configuration in Figure 10 (b). The peak-peak

input voltage is 4 V.

The output code of the ADCs is typically given by:

ADCx

= 10,600 ×

2.5

V REFIN









−VxN

()

ANALOG

INPUT

3.5 V

REF

= 2.5 V

1.5V

0xAD30

0x0000

0x52D0

V1N

ADC CODE

ANALOG

INPUT

4.5 V

REF

= 2.5 V

0.5V

0xAD30

0x0000

0x52D0

V1N

ADC CODE

(a)

(b)

Figure 10. (a) Typical Transfer Characteristic of the ADC

in Differential Input Configuration (b) Typical Transfer

Characteristic of the ADC in Single-Ended

PWMTM

PWMCHA

PWMSYNC

CONVST

PWMSYNC

CONVST

PWMSYNC

CONVST

PWMSYNC

PWMTM/3

(a)

(b)

(c)

(d)

TOFFSET

PWMTM/3

PWMTM

PWMCHA

PWMTM

PWMCHA

PWMTM

TOFFSET

Figure 9. (a) Synchronization of ADC and PWM at Same

Frequency with No Offset, (b) Synchronization of ADC and

PWM at Same Frequency with Offset, (c) Synchronization

of ADC and PWM with No Offset and ADC Update at

Three Times the PWM Frequency (d) Synchronization of

ADC and PWM at Different Frequencies with Offset (PWM

Is Operating in Single Update Mode)

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