ADMC300

–39–

REV. B

AUXTIM1 (W)

DM (0x2011)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

AUXTIM0 (W)

DM (0x2010)

AUX0 DUTY CYCLE = AUXTIM0/256

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

AUX1 DUTY CYCLE = AUXTIM1/256

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7654

3

2

1

0

ETUA0 (R)

ETUB0 (R)

ETUAA0 (R)

ETUA1 (R)

ETUB1 (R)

ETUAA1 (R)

ETUTIME (R)

DM (0x2050)

DM (0x2051)

DM (0x2052)

DM (0x2053)

DM (0x2054)

DM (0x2055)

DM (0x2056)

ETUCONFIG (R/W)

DM (0x205C)

ETU1 EVENT A

ETU1 EVENT B

ETU1 INTERRUPT

ETU1 MODE

ETU0 EVENT A

ETU0 EVENT B

ETU0 INTERRUPT

ETU0 MODE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0 = FALLING EDGE

1 = RISING EDGE

0 = FALLING EDGE

1 = RISING EDGE

0 = NEXT EVENT A

1 = EVENT B

0 = SINGLE-SHOT

1 = FREE-RUNNING

0 = FALLING EDGE

1 = RISING EDGE

0 = FALLING EDGE

1 = RISING EDGE

0 = NEXT EVENT A

1 = EVENT B

0 = SINGLE-SHOT

1 = FREE-RUNNING

ETUDIVIDE (R/W)

DM (0x205D)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

00

0

0

00

0

ETUSTAT (R)

DM (0x205E)

ETU1

ETU0

0 = NOT CAPTURED

1 = SEQUENCE CAPTURED

0 = NOT CAPTURED

1 = SEQUENCE CAPTURED

DM (0x205F)

ETU1

ETU0

ETUCTRL (R/W)

0 = DO NOT START

1 = START CAPTURE

0 = DO NOT CAPTURE

1 = START CAPTURE

0

0

0

0

0

0

0

00

0

0

00

0

0

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 26. Configuration of ADMC300 Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a

gray field – these bits should always be written as shown.