ADAS3022

Data Sheet

Rev. A | Page 34 of 40

CS

n

n

x

x

n

n – 1

n + 2

n + 3

SDO

DIN

SCK

CNV

BUSY

SOC

SOC

EOC

n + 1

x

n + 1

n

n + 3

Figure 71. Data Access Spanning Conversion

GENERAL TIMING

Figure 72 is a general timing diagram showing the complete

register to conversion and readback pipeline delay. The figure

details the timing upon power-up or upon returning from a full

power-down by use of the PD input. Figure 73 and Figure 74 show

the general timing diagrams when only the auxiliary ADC input

channel pair is enabled for the data read during conversion (RDC)

mode and the read after conversion (RAC) mode, respectively.

ACQUISITION (n)

UNDEFINED

PHASE

POWER

UP

CONVERSION (n – 1)

UNDEFINED

CNV

BUSY

DIN

CS

SDO

NOTES

1. DATA ACCESS CAN OCCUR DURING A CONVERSION (

THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC).

2. DATA ACCESS CAN ALSO OCCUR UP TO

TIME CAN BE USED TO ACQUIRE DATA.

3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO

READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION.

4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE.

5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME

OF THE APERTURE DELAY (

DATA

INVALID

SCK

1

1

1

16/32

16

16

X

16

NOTE 3

NOTE 1

NOTE 2

NOTE 2

NOTE 1

NOTE 4

NOTE 5

CFG

INVALID

CFG (n + 2)

DATA (n – 1)

INVALID

ACQUISITION (n + 1)

UNDEFINED

CONVERSION (n)

UNDEFINED

DATA (n – 1)

INVALID

CFG (n + 2)

CFG (n + 3)

DATA (n)

INVALID

ACQUISITION

(n + 2)

CONVERSION (n + 1)

UNDEFINED

DATA (n)

INVALID

CFG (n + 3)

CFG (n + 4)

DATA (n + 1)

INVALID

ACQUISITION

(n + 3)

PHASE

CONVERSION

(n + 2)

CNV

BUSY

DIN

CS

SDO

DATA (n + 1)

INVALID

SCK

1

1

CFG (n + 4)

CFG (n + 5)

DATA (n + 2)

ACQUISITION

(n + 4)

CONVERSION

(n + 3)

DATA (n + 2)

CFG (n + 5)

CFG (n + 6)

DATA (n + 3)

CONVERSION

(n + 4)

DATA (n + 3)

CFG (n + 6)

EOC

EOC

EOC

EOC

EOC

SOC

SOC

Figure 72. General Timing Diagram