ADAS3022BCPZ datasheet(32/40 Pages) AD

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ADAS3022

Data Sheet

Rev. A | Page 32 of 40

RESET AND POWER-DOWN (PD) INPUTS

The asynchronous RESET and PD inputs can be used to reset

and power down the ADAS3022, respectively. Timing details

are shown in Figure 67.

A rising edge on RESET or PD aborts the conversion process and

places SDO into high impedance, regardless of the CS level. Note

that RESET has a minimum pulse width (active high) time for

setting the ADAS3022 into the reset state. See the Configuration

returns from the reset state. If the default setting is used after

RESET is deasserted (Logic 0), a period equal to the acquisition

time (tACQ) must elapse before CNV can be asserted for the

conversion result to be valid. If a conversion is initiated, the

result will be corrupted. In addition, the output data from the

previous conversion is cleared upon a reset. Attempting to

access the data result prior to initiating a new conversion results

in an invalid result.

When the device returns from power-down mode or from a reset

and the default CFG is not used, there is no tACQ requirement;

the first two conversions from power-up are undefined/invalid

because the two-deep delay pipeline requirement must be satisfied

to reconfigure the device to the desired setting.

SDO

CNV

n – 1

SEE NOTE

n – 1

n – 2

BUSY

RESET/

ACQ

DIS

CFG

n + 1

n + 2

NOTES

1. WHEN THE PART IS RELEASED FROM RESET,

tACQ MUST BE MET FOR

CONVERSION n IF USING THE DEFAULT CFG SETTING FOR CHANNEL IN0.

WHEN THE PART IS RELEASED FROM POWER-DOWN,

tACQ IS NOT REQUIRED,

AND THE FIRST TWO CONVERSIONS, n AND n + 1, ARE UNDEFINED.

Figure 67. RESET and PD Timing

SERIAL DATA INTERFACE

The ADAS3022 uses a simple 4-wire interface and is compatible

with FPGAs, DSPs, and common serial interfaces, such as SPI,

QSPI, and MICROWIRE™. The interface uses the CS, SCK,

SDO, and DIN signals. Timing details for the serial interface are

shown in Figure 68. SDO is activated when CS is asserted. The

conversion result is output on SDO and is updated on SCK

falling edges. Simultaneously, the 16-bit CFG word is updated, if

desired, on the serial data input (DIN). The state of the clock

phase select bit (CPHA, Bit 0) determines whether the MSB is

output again on the first clock or whether the MSB − 1 bit is

output when SDO is activated after the EOC.

Note that in Figure 67 and Figure 68, SCK is shown idling high.

SCK can idle high or low, requiring that the system developer

design an interface that suits setup and hold times for both SDO

and DIN.

DIN

(MOSI)

SDO

(MISO)

SCK

tEN

tSDOD

tSDOH

tSCK

tDIS

tDINH

tDINS

tSCKH

tSCKL

Figure 68. Serial Timing

CPHA

The clock phase select bit (CPHA, Bit 0) sets the first bit of the

conversion result on SDO after the end of a conversion (see

Figure 69).

Setting CPHA to 0 outputs the MSB when CS is asserted. Sub-

sequent SCK falling edges clock out bits in an MSB − 1, MSB − 2,

and so on fashion. This mode is useful for hosts limited to 16 clock

edges where the first falling (or rising) edge can be used to latch

the data.

Setting CPHA to 1 outputs the MSB not only when CS is asserted

but also after the first SCK falling edge. Subsequent SCK falling

edges clock out bits in an MSB − 1, MSB − 2, and so on fashion.

This mode can be useful for sign extension applications.

SDO

CPHA = 1

SDO

CPHA = 0

SCK

MSB

LSB

LSB + 1

MSB – 1

MSB – 2

MSB

LSB + 1

LSB

LSB + 2

MSB

MSB – 1

Figure 69. CPHA Details

Sampling on the SCK Falling Edge

To achieve the fastest data transfer rate, the host should sample

data on the SCK falling edge, as long as there is a sufficient hold

time of ≤tSDOH (see Figure 68). When using this method, data

transfers should occur during the safe conversion time (tDDC).

Because this time is fixed, extending data reading or writing into

the quiet conversion phase (tQUIET) may cause data corruption.

However, for systems that need slightly more time, tDDCA (data

during conversion additional) can be used.

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