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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9884A датащи(PDF) 2 Page - Analog Devices |
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AD9884A датащи(HTML) 2 Page - Analog Devices |
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2 / 24 page  REV. B –2– AD9884A–SPECIFICATIONS (VD = +3.3 V, VDD = +3.3 V, PVD = +3.3 V, ADC Clock Frequency = Maximum, PLL Clock Frequency = Maximum, Control Registers Programmed to Default State) Test AD9884AKS-100 AD9884AKS-140 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity +25 °CI ±0.5 ±1.0 ±0.5 +1.15/–1.0 LSB Full VI ±1.0 +1.25/–1.0 LSB Integral Nonlinearity +25 °CI ±0.5 ±1.25 ±0.8 ±1.4 LSB Full VI ±1.75 ±2.5 LSB No Missing Codes Full VI Guaranteed Guaranteed ANALOG INPUT Input Voltage Range Minimum Full VI 0.5 0.5 V p-p Maximum Full VI 1.0 1.0 V p-p Gain Tempco +25 °C V 100 280 ppm/ °C Input Bias Current +25 °CI 1 1 µA Full VI 1 1 µA Input Offset Voltage Full VI 7 50 7 50 mV Input Full-Scale Matching Full VI 1.5 5.0 1.5 5.0 %FS Offset Adjustment Range Full VI 22 23.5 25 22 23.5 25 %FS REFERENCE OUTPUT Output Voltage Full VI +1.20 +1.25 +1.30 +1.20 +1.25 +1.30 V Temperature Coefficient Full V ±50 ±50 ppm/ °C SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 100 140 MSPS Minimum Conversion Rate Full IV 10 10 MSPS Data to Clock Skew, tSKEW Full IV –0.5 +2.0 –0.5 +2.0 ns tBUFF Full VI 4.7 4.7 µs tSTAH Full VI 4.0 4.0 µs tDHO Full VI 0 0 µs tDAL Full VI 4.7 4.7 µs tDAH Full VI 4.0 4.0 µs tDSU Full VI 250 250 ns tSTASU Full VI 4.7 4.7 µs tSTOSU Full VI 4.0 4.0 µs HSYNC Input Frequency Full IV 15 110 15 110 kHz Maximum PLL Clock Rate Full VI 100 140 MHz Minimum PLL Clock Rate Full IV 20 20 MHz PLL Jitter +25 °C IV 400 700 1 475 750 2 ps p-p Full IV 1000 1 1000 2 ps p-p Sampling Phase Tempco Full IV 15 15 ps/ °C DIGITAL INPUTS Input Voltage, High (VIH) Full VI 2.5 2.5 V Input Voltage, Low (VIL) Full VI 0.8 0.8 V Input Current, High (IIH) Full VI –1.0 –1.0 µA Input Current, Low (IIL) Full VI 1.0 1.0 µA Input Capacitance +25 °CV 3 3 pF DIGITAL OUTPUTS Output Voltage, High (VOH) Full VI VDD – 0.1 VDD – 0.1 V Output Voltage, Low (VOL) Full VI 0.1 0.1 V Duty Cycle DATACK, DATACK Full IV 45 50 55 45 50 55 % Output Coding Binary Binary |
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