AD9884A datasheet(13/24 Pages) AD

13 / 24 page

REV. B

AD9884A

–13–

Writing data to specific control registers of the AD9884A requires

that the 8-bit address of the control register of interest be written

after the slave address has been established. This control register

address is the base address for subsequent write operations. The

base address autoincrements by one for each byte of data written

after the data byte intended for the base address. If more bytes

are transferred than there are available addresses, the address

will not increment and remain at its maximum value of 0Eh. Any

base address higher than 0Eh will not produce an ACKnowledge

signal.

Data are read from the control registers of the AD9884A in a

similar manner. Reading requires two data transfer operations:

The base address must be written with the R/

W bit of the slave

address byte LOW to set up a sequential read operation.

Reading (the R/

W bit of the slave address byte HIGH) begins at

the previously established base address. The address of the read

To terminate a read/write sequence to the AD9884A, a stop

signal must be sent. A stop signal comprises a LOW-to-HIGH

transition of SDA while SCL is HIGH.

A repeated start signal occurs when the master device driving

the serial interface generates a start signal without first generat-

ing a stop signal to terminate the current communication. This is

used to change the mode of communication (read, write) between

the slave and master without releasing the serial interface lines.

Serial Interface Read/Write Examples

Write to One Control Register

• Start Signal

• Slave Address Byte (R/

W Bit = LOW)

• Base Address Byte

• Data Byte to Base Address

• Stop Signal

tSTOSU

tDAH

SDA

SCL

tBUFF

tSTAH

tDHO

tDSU

tDAL

tSTASU

Figure 1. Serial Port Read/Write Timing

SDA

SCL

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ACK

Figure 2. Serial Interface—Typical Byte Transfer

Write to Four Consecutive Control Registers

• Start Signal

• Slave Address Byte (R/

W Bit = LOW)

• Base Address Byte

• Data Byte to Base Address

• Data Byte to (Base Address + 1)

• Data Byte to (Base Address + 2)

• Data Byte to (Base Address + 3)

• Stop Signal

Read from One Control Register

• Start Signal

• Slave Address Byte (R/

W Bit = LOW)

• Base Address Byte

• Start Signal

• Slave Address Byte (R/

W Bit = HIGH)

• Data Byte from Base Address

• Stop Signal

Read from Four Consecutive Control Registers

• Start Signal

• Slave Address Byte (R/

W Bit = LOW)

• Base Address Byte

• Start Signal

• Slave Address Byte (R/

W Bit = HIGH)

• Data Byte from Base Address

• Data Byte from (Base Address + 1)

• Data Byte from (Base Address + 2)

• Data Byte from (Base Address + 3)

• Stop Signal

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