AD9816

–8–

REV. A

DEFINITIONS OF SPECIFICATIONS

INTEGRAL NONLINEARITY (INL)

Integral nonlinearity error refers to the deviation of each indi-

vidual code from a line drawn from “zero scale” through “posi-

tive full scale.” The point used as “zero scale” occurs 1/2 LSB

before the first code transition. “Positive full scale” is defined as

a level 1 1/2 LSB beyond the last code transition. The deviation

is measured from the middle of each particular code to the true

straight line.

DIFFERENTIAL NONLINEARITY (DNL)

An ideal ADC exhibits code transitions which are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Thus every

code must have a finite width. No missing codes guaranteed to

12-bit resolution indicates that all 4096 codes, respectively,

must be present over all operating ranges.

OFFSET ERROR

The first ADC code transition should occur at a level 1/2 LSB

above the nominal zero scale voltage. The offset error is the

deviation of the actual first code transition level from the ideal

level.

GAIN ERROR

The last code transition should occur for an analog value

1 1/2 LSB below the nominal full scale voltage. Gain error is

the deviation of the actual difference between first and last code

transitions and the ideal difference between the first and last

code transitions.

TOTAL OUTPUT NOISE

An ideal ADC outputs only one code value for a dc input

voltage. A real converter has noise sources that will cause a

spread of codes at the output for a dc input voltage. The total

output noise is measured with a grounded input and is equal to

the standard deviation of the histogram of output codes.

CHANNEL-TO-CHANNEL CROSSTALK

In an ideal three-channel system, the signal in one channel will

not influence the signal level of another channel. The channel-

to-channel crosstalk specification is a measure of the change that

occurs in one channel as the other two channels are varied. In

the AD9816, one channel is grounded and the other two chan-

nels are exercised with full-scale input signals. The change in

the output codes from the first channel is measured and com-

pared with the result when all three channels are grounded. The

difference is the channel-to-channel crosstalk, stated in LSBs.

APERTURE DELAY

The aperture delay is the time delay that occurs from when a

sampling edge is applied to the AD9816 until the actual sample

of the input signal is held. For CDSCLK1, the aperture delay

represents the amount of time it takes for the clamp switch

to open after CDSCLK1 transitions from high to low. For

CDSCLK2, the aperture delay is the amount of time after the

CDSCLK2 falling edge that the input signal is sampled.

POWER SUPPLY REJECTION

Power supply rejection specifies the maximum full-scale change

that occurs from the initial value when the supplies are varied

over the specified limits.

FUNCTIONAL DESCRIPTION

The AD9816 can be operated in several different modes:

3-channel CDS mode, 3-channel SHA mode, 1-channel CDS

mode, and 1-channel SHA mode. Each mode is selected by

programming the Configuration Register through the serial

interface. For more detail on CDS or SHA mode operation, see

Circuit Descriptions section.

3-Channel CDS Mode

In 3-channel CDS mode, the AD9816 simultaneously samples

the red, green and blue input voltages from the CCD outputs.

The sampling points for each Correlated Double Sampler (CDS)

are controlled by CDSCLK1 and CDSCLK2. CDSCLK1’s fall-

ing edge clamps the reference level of the CCD waveform at the

analog inputs of the AD9816. CDSCLK2’s falling edge samples

the data level of the CCD waveform. Each CDS amplifier out-

puts the difference between the CCD reference and data levels.

Next, the output voltage of each CDS amplifier is level-shifted

by an Offset DAC. The voltages are then scaled by the three

Programmable Gain Amplifiers before being multiplexed to the

common 12-bit ADC. The ADC sequentially samples the PGA

outputs on the falling edges of ADCCLK.

Timing for this mode is shown in Figure 1, using a 2

× master

clock. Although it is not required, it is recommended that the

falling edge of CDSCLK2 be aligned with the rising edge of

ADCCLK. The rising edge of CDSCLK2 should not occur

The maximum allowable width of CDSCLK2 will be dependent

on the ADCCLK period, and equal to one ADCCLK period

minus 30 ns. The output data latency is three clock cycles.

The offset and gain values for the red, green, and blue channels

are programmed using the serial interface. The order in which

the channels are switched through the multiplexer is selected by

programming the MUX register. The rising edge of CDSCLK2

always resets the multiplexer.

3-Channel SHA Mode

In 3-channel SHA mode, the AD9816 simultaneously samples

the red, green, and blue input voltages. The sample-and-hold

amplifier’s sampling point is controlled by CDSCLK2. CDSCLK2’s

falling edge samples the input waveforms on each channel. The

output voltages from the three SHAs are modified by the offset

DACs and then scaled by the three PGAs. The outputs of the

PGAs are then multiplexed through the 12-bit ADC. The ADC

sequentially samples the PGA outputs on the falling edges of

ADCCLK.

The input signal is sampled with respect to the voltage applied

to the OFFSET pin. With the OFFSET pin grounded, a zero

volt input corresponds to the ADC’s zero scale output. The

input clamp is disabled in this mode. However, the OFFSET

pin may be used as a coarse offset adjust pin. A voltage applied

to this pin will be subtracted from the voltages applied to the

red, green and blue inputs in the first amplifier stage of the

AD9816. For more information, see the Circuit Descriptions

section.

Timing for this mode is shown in Figure 2, using a 1

× master

clock. CDSCLK1 should be grounded in this mode. Although

it is not required, it is recommended that the falling edge of

CDSCLK2 be aligned with the rising edge of ADCCLK. The

rising edge of CDSCLK2 should not occur before the previous

allowable width of CDSCLK2 will be dependent on the ADCCLK