AD9775EB datasheet(17/48 Pages) AD

17 / 48 page

REV. 0

AD9775

–17–

R/W

Bit 7 of the instruction byte determines whether a read or a

write data transfer will occur after the instruction byte write.

Logic high indicates read operation. Logic “0” indicates a write

operation.

N1, N0

Bits 6 and 5 of the instruction byte determine the number of

bytes to be transferred during the data transfer cycle. The bit

decodes are shown in the following table:

MSB

LSB

R/W

A4, A3, A2, A1, A0

Bits 4, 3, 2, 1, and 0 of the instruction byte determine which

munications cycle. For multibyte transfers, this address is the

starting byte address. The remaining register addresses are

generated by the AD9775.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SCLK (Pin 55)—Serial Clock

The serial clock pin is used to synchronize data to and from the

AD9775 and to run the internal state machines. SCLK maxi-

mum frequency is 15 MHz. All data input to the AD9775 is

registered on the rising edge of SCLK. All data is driven out of

the AD9775 on the falling edge of SCLK.

CSB (Pin 56)—Chip Select

Active low input starts and gates a communication cycle. It

allows more than one device to be used on the same serial com-

munications lines. The SDO and SDIO pins will go to a high

impedance state when this input is high. Chip select should stay

low during the entire communication cycle.

SDIO (Pin 54)—Serial Data I/O

Data is always written into the AD9775 on this pin. However,

this pin can be used as a bidirectional data line. The configura-

tion of this pin is controlled by Bit 7 of Register Address 00h.

The default is Logic “0,” which configures the SDIO Pin as

unidirectional.

SDO (Pin 53)—Serial Data Out

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. In the case where the AD9775

operates in a single bidirectional I/O mode, this pin does not

output data and is set to a high impedance state.

MSB/LSB TRANSFERS

The AD9775 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by Register Address 00h, Bit 6. The

default is MSB first. When this bit is set active high, the AD9775

serial port is in LSB first format. That is, if the AD9775 is in

LSB first mode, the instruction byte must be written from least-

significant bit to most significant bit. Multibyte data transfers in

MSB format can be completed by writing an instruction byte

that includes the register address of the most significant byte. In

MSB first mode, the serial port internal byte address generator

decrements for each byte required of the multibyte communica-

tion cycle. Multibyte data transfers in LSB first format can be

completed by writing an instruction byte that includes the regis-

ter address of the least significant byte. In LSB first mode, the

serial port internal byte address generator increments for each

byte required of the multibyte communication cycle.

The AD9775 serial port controller address will increment from

1Fh to 00h for multibyte I/O operations if the MSB first mode is

active. The serial port controller address will decrement from 00h

to 1Fh for multibyte I/O operations if the LSB first mode is active.

SCLK

SDIO

SDO

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

R/W

D7N

D6N

D7N

D6N

D00

D10

D20

D00

D10

D20

(N)

Figure 3a. Serial Register Interface Timing MSB First

SCLK

SDIO

SDO

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

R/W

D7N

D6N

D7N

D6N

D00

D10

D20

D00

D10

D20

(N)

Figure 3b. Serial Register Interface Timing LSB First

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