AD9501

REV. A

–8–

For most applications, OUTPUT can be tied to RESET. This

causes the output pulse to be narrow (equal to the Reset

applied to RESET. To assure a valid output pulse, however, the

delay between TRIGGER and RESET should be equal to or

timing diagram Figure 1.

As shown in that figure, the capacitor voltage discharges very

rapidly and includes a small amount of overshoot and ringing.

Rated timing delay will not be realized unless subsequent trigger

events are delayed until after the linear ramp settles to its reset

voltage value.

The values for the various delay increments in the specification

table are based on a Full-Scale Delay Range of 100 ns with

OUTPUT tied to RESET (self-resetting operation).

When Full-Scale Delay Range is set for intervals shorter than

100 ns, the rate of change of the linear ramp is increased. This

faster rate means the Maximum Trigger Rate shown in the

specification table is increased because the Ramp Generator

become smaller.

Scale Delay Range is decreased. Minimum Delays for various

Full-Scale Delay Range values are shown in Figure 2.

APPLICATIONS

The AD9501 is useful in a wide variety of precision timing

applications because of its ability to delay TTL/ CMOS pulse

edges by increments as small as 10 ps.

Figure 4. AD9501 Typical Circuit Configuration

In Figure 4, the AD9501 typical circuit configuration, the

delayed output is tied back to the RESET input. This will pro-

duce a narrow output pulse whose leading edge is delayed by an

amount proportional to the 8-bit digital word stored in the on-

board latches. For the configuration shown, the output pulse

wider pulses are required, a delay can be inserted between

OUTPUT and RESET. If preferred, an external pulse can be

used as a reset input to control the timing of the falling edge

(and consequently, the width) of the delayed output.

Multiple Signal Path Deskewing

High speed electronic systems with parallel signal paths require

that close delay matching be maintained. If delay mismatch

(time skew) occurs, errors can occur during data transfer. For

these situations, the matching of delays is generally accom-

plished by carefully matching lead lengths.

Figure 5. Multiple Signal Path Deskewing