AD9501

REV. A

–7–

Ramp charging current and DAC full-scale current are slaved

together in the AD9501 to minimize delay drift over tempera-

which are used should be 1% metal film types.

The minimum delay through the AD9501 corresponds to an

programmed delay can be approximated by:

Total delay through the AD9501 for any given DAC code is

equal to:

As shown on the block diagram, TTL/CMOS latches are

included to store the digital delay data. Data is latched when

LATCH is HIGH. When LATCH is LOW, the latches are

transparent, and the DAC will attempt to follow any changes on

The System Timing Diagram, Figure 3, shows the timing

relationship between the input data and the latch. The DAC

(Programmed Delay) data is updated, a minimum 30 ns must

elapse between the time LATCH goes high and the arrival of a

TRIGGER pulse to assure rated pulse delay accuracy.

8.5 pF) is discharged. The RESET input is level-sensitive, and

overrides the TRIGGER input. Therefore, any trigger pulse

which occurs when RESET is HIGH will not produce an output

pulse. As shown on the system timing diagram, Figure 3, the

next trigger pulse should not occur before the Linear Ramp

delay accuracy.

Figure 3. AD9501 System Timing