AD9260AS datasheet(27/36 Pages) AD

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AD9260

–27–

REV. B

The scaling is accomplished by properly attaching an external

resistor to the BIAS pin of the AD9260 as shown in Table IX.

REXT is normally 2 k

Ω for a clock speed of 20 MHz and scales

inversely with clock rate. Because BIAS is an external pin, mini-

mization of capacitance to this pin is recommended in order to

prevent instability of the bias pin amplifier.

AVDD

MODE PIN

AVSS

LATCH

CLOCK

ENCODED MODE

Figure 62. Simplified Mode Pin Circuitry

BIAS CURRENT

REXT

BIAS PIN

Figure 63. Simplified Bias Pin Circuitry

POWER DISSIPATION CONSIDERATIONS

The power dissipation of the AD9260 is dependent on its

application-specific configuration and operating conditions.

The analog power dissipation as shown in Figure 64 is primarily

a function of its power bias setting and sample rate. It remains

insensitive to the particular input waveform being digitized or

digital filter MODE setting. The digital power dissipation is

primarily a function of the digital supply setting (i.e., +3 V to

+5 V), the sample rate and, to a lesser extent, the MODE setting

and input waveform. Figures 65a and 65b show the total current

dissipation of the “combined” digital (DVDD) and digital driver

supply (DRVDD) for +3 V and +5 V supplies. Note, DVDD

and DRVDD are typically derived from the same supply bus

since no degradation in performance results. A 1 MHz full-

scale sine wave was used to ensure maximum digital activity in

the digital filters and the digital drivers had a fanout of one.

Note also that a twofold decrease in digital supply current re-

sults when the digital supply is reduced form +5 V to +3 V.

SAMPLE RATE – MSPS

110

130

FULL BIAS-2k

HALF BIAS-4k

QUARTER BIAS-8k

Figure 64. IAVDD vs. Sample Rate (AVDD = +5 V,

Mode 1

×–4×)

SAMPLE RATE – MSPS

Figure 65a. IDVDD/IDRVDD vs. Sample Rate (DVDD = DRVDD =

3 V, fIN = 1 MHz)

SAMPLE RATE – MSPS

Figure 65b. IDVDD/IDRVDD vs. Sample Rate (DVDD = DRVDD

= 5 V, fIN = 1 MHz)

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