AD9054

–13–

REV. 0

the specification table. In this case the DS hold time specifica-

tion on the rising edge can be ignored.

Applications that will continuously update the synchronization

command need to treat the DS signal as a pulse and satisfy

timing requirements on both rising and falling edges. It is easiest

to consider the DS signal in this case to be a pulse train at one

half the encode rate, the positive pulse nominally bracketing the

ENCODE falling edge on alternate cycles as shown in the tim-

ing diagram (Figure 2). The falling/rising edge of DS has to

edge of ENCODE; similarly, the rising/falling edge of DS has to

falls. This timing requirement produces a tight timing window

at higher encode rates. Synchronization by a single reset edge

results in a simpler timing solution in many applications. For

example, synchronization may be provided at the beginning of

each graphics line or frame.

The data are presented at the output of the AD9054 in a ping-

pong (alternating) fashion to optimize the performance of the

converter. It may be aligned for presentation as sixteen bits in

parallel by adding a register stage to the output.

In Dual Channel Mode, the converted data is produced five

clock cycles after the rising edge of ENCODE on which the

sample is taken (five pipeline delays).

VIN

0.1 F

1k

0.1 F

0.1 F

NC

CLOCK

VREF OUT

VREF IN

AIN

AIN

DEMUX

AD9054

DS

DS ENC ENC

A PORT

DS

'573

B PORT

'74

DIVIDE

BY 2

NC = NO CONNECT

Figure 36. Dual Port Mode—Aligned Output Data

In Figure 36, the converter is operating in Dual Port Mode,

with data coming alternately out of Port A and Port B. The

figure illustrates how the output data may be aligned with an

output latch to produce a 16-bit output at 1/2 the conversion

clock rate. The Data Sync input must be properly exercised to

time the A Port with the synchronizing latch.