MSC8152 datasheet(48/68 Pages) FREESCALE

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MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 5

Electrical Characteristics

Freescale Semiconductor

2.6.5

Ethernet Timing

This section describes the AC electrical characteristics for the Ethernet interface.

There are programmable delay units (PDU) that should be programmed differently for each interface to meet timing. There is

a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8152 Reference

Manual.

2.6.5.1

Management Interface Timing

Table 33 lists the timer input Ethernet controller management interface timing specifications shown in Figure 24.

Table 33. Ethernet Controller Management Interface Timing

Characteristics

Symbol

Min

Max

Unit

GE_MDC frequency

fMDC

—2.5

MHz

GE_MDC period

tMDC

400

—

GE_MDC clock pulse width high

tMDC_H

160

—

GE_MDC clock pulse width low

tMDC_L

160

—

GE_MDC to GE_MDIO delay2

tMDKHDX

GE_MDIO to GE_MDC rising edge setup time

tMDDVKH

—

GE_MDC rising edge to GE_MDIO hold time

tMDDXKH

0—

Notes:

Program the GE_MDC frequency (fMDC) to a maximum value of 2.5 MHz (400 ns period for tMDC). The value depends on the

source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz to

achieve fMDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8152 Reference Manual for

configuration details.

The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of

333 MHz, the delay is 58 ns.

Figure 24. MII Management Interface Timing

GE_MDC

GE_MDIO

(Input)

(Output)

tMDC

tMDDXKH

tMDDVKH

tMDKHDX

tMDC_H

tMDC_L

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