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AD8401 датащи(PDF) 4 Page - Analog Devices

номер детали AD8401
подробное описание детали  8-Bit, 4-Channel Data Acquisition System
PDF  12 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD8401 датащи(HTML) 4 Page - Analog Devices

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AD8401
–4–
REV. 0
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8401 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING ELECTRICAL SPECIFICATIONS
(@ VDD = +5.0 V
5%, AGDAC = AGADC = 0.0 V; fCLK = 5 MHz; –40 C ≤ TA ≤ +85 C,
unless otherwise noted)
Parameters
1, 2, 3
Symbol
Condition
Min
Typ
Max
Units
DAC TIMING (See Figure 8 Timing Diagram)
WR
Pulse Width
t1
50
ns
CS
to WR Setup Time
t2
0ns
CS
to WR Hold Time
t3
0ns
Data Setup Time
t4
60
ns
Data Hold Time
t5
0ns
ADC TIMING (See Figures 6 and 7 Timing Diagrams)
ST
Pulse Width
t6
40
ns
ST
to BUSY Delay
t7
110
ns
BUSY
to INT Delay
t8
30
ns
BUSY
to CS Delay
t9
0ns
CS
to RD Setup Time
t10
0ns
RD
Pulse Width
4
t11
75
ns
CS
to RD Hold Time
t12
0ns
Data Access after RD
t13
CL = 20 pF
10
75
ns
Data Access after RD
t13
CL = 100 pF
10
135
ns
Bus Relinquish after RD
t14
10
70
ns
RD
to INT Delay
t15
85
ns
RD
to BUSY Delay
t16
110
ns
Data Valid after BUSY
t17
CL = 20 pF
90
ns
Data Valid after BUSY
t17
CL = 100 pF
135
ns
NOTES
1All input control signals are specified with t
R = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2t
13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3t
14 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
4t
15 is determined by t13.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V
Input Voltages . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/
θ
JA
Thermal Resistance
θ
JA
28-Lead SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . 53
°C/W
Storage Temperature Range . . . . . . . . . . . . –65
°C to +150°C
Operating Temperature Range . . . . . . . . . . . . –40
°C to +85°C
Junction Temperature Range (TJ max) . . . . –65
°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . +300
°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Package
Package
Model*
Range
Description
Option
AD8401AR
–40
°C to +85°C 28-Lead SOIC SOL-28
AD8401Chips
+25
°C
Die
*The AD8401 contains 1257 transistors.
Figure 1. Load Circuits for Data Access Time Test
a. VOH to High Z
a. High Z to VOH
b. High Z to VOL
DGND
CL
3k
DBN
DBN
CL
3k
+5V
DGND
DGND
10pF
3k
DBN
DBN
10pF
3k
+5V
DGND
b. VOL to High Z
Figure 2. Load Circuits for Bus Relinquish Time Test



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