AD8401

–7–

REV. 0

BUSY

INT

CS

RD

DATA

NEW DATA

HIGH Z

OLD DATA

Figure 7. Mode 2, ADC Interface Timing

Mode 2 Interface

This interface mode can be used with microprocessors that can

be put into a WAIT state for at least 2 microseconds. The ST

pin must be tied to logic high for proper operation. The micro-

processor begins a conversion by executing a READ instruction

that asserts the CS and RD pins at the AD8401’s decoded ad-

dress. The AD8401 BUSY output then goes low, forcing the

microprocessor’s READY (or WAIT) line into a WAIT state.

The analog input signal is captured by the T/H on the falling

edge of RD. When the conversion is complete (8 clocks later),

the BUSY line returns high, and then the

µP completes its

READ of the new data now on the digital output port of the

AD8401. Note that while conversion is in progress the ADC

places the results from the last conversion (Old Data) on the

data bus. The Figure 7 timing diagram details the applicable

timing specification requirements.

DIGITAL INTERFACE: DAC TIMING AND CONTROL

Table II shows the truth table for DAC operation. The internal

8-bit DAC register contents are loaded from the data bus when

both WR and CS are asserted. The DAC register determines the

D/A converter analog-output voltage. The WR input is a posi-

tive edge triggered input that loads the bus data into the DAC

register subject to the data setup and data hold timing require-

ments. When CS and WR are low, the DAC register contents

will not change with changing data bus values. Figure 8 provides

the detail timing diagram for write cycle operation.

Table II. DAC Register Logic

CS

WR

RS

DAC Function

H

H

H

No Effect

L

L

H

No Effect

L

H

DAC Register Updated

L

H

DAC Register Updated

X

X

L

DAC Register Loaded with all Zeros

CS

WR

DATA

VALID DATA

Figure 8. Write Cycle Timing

CLOCK

The AD8401 uses an external clock that is TTL or 5 V CMOS

compatible. The external clock speed is 5 MHz and the duty

cycle may vary from 30% to 70%. The external clock can be

continuously operated between conversions.

DIGITAL INTERFACE: ADC TIMING AND CONTROL

Two basic ADC operating modes are available with the

AD8401. The first mode uses the Start (ST) pin to trigger a

synchronized A/D conversion. As soon as the ST pin is asserted,

the T/H switches from tracking to the hold mode capturing the

present analog input-voltage sample. With the T/H holding the

analog sample the successive-approximation analog-to-digital

conversion is completed on that sample value. At the end of

conversion the T/H returns to the tracking mode. This mode of

conversion is ideal for digital signal processing applications

where precise interval sampling is necessary to minimize errors

due to sampling uncertainty or jitter. A precise clock source can

be used to drive the ST input.

The second mode of conversion is started by the RD and CS in-

puts going low, after which the BUSY line puts the micropro-

cessor into a WAIT state until end of conversion. Mode 2 is

asserted by connecting the ST pin to logic high. The major ad-

vantage of this interface is that a single Read Instruction will

start and complete a new analog-to-digital conversion without

the need for carefully tailored software delays that often are not

portable when software routines are taken to a different proces-

sor running at a different clock speed.

BUSY

ST

INT

CS

RD

DATA

DATA VALID

HIGH Z

Figure 6. Mode 1, ADC Interface Timing

Mode 1 Interface

As shown in Figure 6, the falling edge of the ST pulse initiates a

conversion and puts the T/H amplifier into the hold mode. The

BUSY

signal goes low during the whole A/D conversion time

and returns high signaling end of conversion. The INT line can

be used to interrupt the microprocessor. When the microproces-

sor performs a READ to access the AD8401 data, the rising

timing specification. INT can also be used to externally trigger a

pulse that activates the CS and RD and places the new data into

a buffer or First In First Out FIFO memory. The microproces-

sor can then load a series of readings from this buffer memory at

a convenient time. Care must be taken not to have the ST input

high when RD is brought low; otherwise, the AD8401 will not

operate properly. Also triggering the ST line a second time be-

fore conversion is complete will cause erroneous readings.