AD8361

–12–

REV. A

Alternatively, a reactive match can be implemented using a shunt

inductor to ground and a series capacitor as shown in Figure

39c. A method for hand calculating the appropriate matching

components is shown on page 12 of the AD8306 data sheet.

especially at high frequencies. As a result, a stray capacitance as

small as 1 pF can significantly degrade the quality of the match.

The main advantage of a reactive match is the increase in sensi-

tivity that results from the input voltage being “gained up” (by

the square root of the impedance ratio) by the matching network.

Table III shows recommended values for reactive matching.

Table III. Recommended Values for a Reactive Input Match

(Figure 39c)

Frequency

MHz

pF

nH

100

16

180

800

2

15

900

2

12

1800

1.5

4.7

1900

1.5

4.7

2500

1.5

3.3

Input Coupling Using a Series Resistor

Figure 39d shows a technique for coupling the input signal

into the AD8361, which may be applicable where the input signal

is much larger than the input range of the AD8361. A series

resistor combines with the input impedance of the AD8361 to

attenuate the input signal. Since this series resistor forms a

divider with the frequency-dependent input impedance, the

apparent gain changes greatly with frequency. However, this

method has the advantage of very little power being “tapped

off” in RF power transmission applications. If the resistor is large

compared to the transmission line’s impedance then the VSWR of

the system is relatively unaffected.

FREQUENCY – MHz

200

0

500

100

0

250

150

50

1000

1500

2000

2500

3000

3500

0.2

0.5

0.8

1.1

1.4

1.7

Figure 40. Input Impedance vs. Frequency, Supply 3 V,

SOT-23-6L

Selecting the Filter Capacitor

The AD8361’s internal 27 pF filter capacitor is connected in

parallel with an internal resistance that varies with signal level

from 2 k

Ω for small signals to 500 Ω for large signals. The

resulting low-pass corner frequency between 3 MHz and 12 MHz

provides adequate filtering for all frequencies above 240 MHz

(i.e., ten times the frequency at the output of the squarer, which

is twice the input frequency). However, signals with high peak-

to-average ratios, such as CDMA or W-CDMA signals, and

with low frequency components, require additional filtering.

TDMA signals, such as GSM, PDC, or PHS have a peak-to-

average ratio that is close to that of a sinusoid, and the internal

filter is adequate.

The filter capacitance of the AD8361 can be augmented by

connecting a capacitor between Pin 6 (FLTR) and VPOS.

Table IV shows the effect of several capacitor values for various

communications standards with high peak-to-average ratios along

with the residual ripple at the output, in peak-to-peak and rms

volts. Note that large filter capacitors will increase the enable

and pulse response times, as discussed below.

Output

Residual AC

Waveform

V dc

mV p-p

mV rms

IS95 Reverse Link

Open

0.5

550

100

1.0

1000

180

2.0

2000

360

0.01

µF

0.5

40

6

1.0

160

20

2.0

430

60

0.1

µF

0.5

20

3

1.0

40

6

2.0

110

18

IS95 8-Channel

0.01

µF

0.5

290

40

Forward Link

1.0

975

150

2.0

2600

430

0.1

µF

0.5

50

7

1.0

190

30

2.0

670

95

W-CDMA 15

0.01

µF

0.5

225

35

Channel

1.0

940

135

2.0

2500

390

0.1

µF

0.5

45

6

1.0

165

25

2.0

550

80

Operation at Low Frequencies

Although the AD8361 is specified for operation up to 2.5 GHz,

there is no lower limit on the operating frequency. It is only nec-

essary to increase the input coupling capacitor to reduce the

corner frequency of the input high-pass filter (use an input resis-

tance of 225

Ω for frequencies below 100 MHz). It is also

necessary to increase the filter capacitor so that the signal at the

output of the squaring circuit is free of ripple. The corner fre-

quency will be set by the combination of the internal resistance of

2 k

Ω and the external filter capacitance.

Power Consumption, Enable and Power-On

The quiescent current consumption of the AD8361 varies with

the size of the input signal from about 1 mA for no signal up to

7 mA at an input level of 0.66 V rms (9.4 dBm re 50

Ω). If the

input is driven beyond this point, the supply current increases

steeply (see Figure 12). There is little variation in quiescent

current with power supply voltage.