AD8313

–14–

REV. B

In addition to providing current gain, the resistor/potentiometer

combination between VSET and the emitter of the transistor

increases the log slope to as much as 45 mV/dB, at maximum

resistance. This will give an output voltage of 4 V for a 0 dBm

input. If no increase in the log slope is required, VSET can be

connected directly to the emitter of the transistor.

Effect of Waveform Type On Intercept

Although it is specified for input levels in dBm (dB relative to

1 mW), the AD8313 fundamentally responds to voltage and not

to power. A direct consequence of this characteristic is that

input signals of equal rms power but differing crest factors will

produce different results at the log amp’s output.

The effect of different signal waveforms is to vary the effec-

tive value of the log amp’s intercept upwards or downwards.

Graphically, this looks like a vertical shift in the log amp’s trans-

fer function. The device’s logarithmic slope, however, is in

principle not affected. For example, consider the case of the

AD8313 being alternately fed from a continuous wave and a

single CDMA channel of the same rms power. The AD8313’s

output voltage will differ by the equivalent of 3.55 dB (64 mV)

over the complete dynamic range of the device (the output for a

CDMA input being lower).

Table III shows the correction factors that should be applied to

measure the rms signal strength of a various signal types. A

continuous wave input is used as a reference. To measure the

rms power of a square-wave, for example, the mV equivalent

of the dB value given in the table (18 mV/dB times 3.01 dB)

should be subtracted from the output voltage of the AD8313.

Table III. Shift in AD8313 Output for Signals with Differing

Crest Factors

Correction Factor

Signal Type

(Add to Output Reading)

CW Sine Wave

0 dB

Square Wave or DC

–3.01 dB

Triangular Wave

+0.9 dB

GSM Channel (All Time Slots On)

+0.55 dB

CDMA Channel

+3.55 dB

PDC Channel (All Time Slots On)

+0.58 dB

Gaussian Noise

+2.51 dB

EVALUATION BOARD

Schematic and Layout

Figure 44 shows the schematic of the evaluation board that was

used to characterize the AD8313. Note that uninstalled compo-

nents are drawn in as dashed.

This is a 3-layer board (signal, ground and power), with a Duroid

dielectric (RT 5880, h = 5 mil,

ε

but microstrip dimensions must be recalculated because of the

different dielectric constant and board height. The trace layout

and silkscreen of the signal and power layers are shown in Fig-

ures 40 to 43. A detail of the PCB footprint for the

µSOIC

package and the pads for the matching components are shown

in Figure 45.

The vacant portions of the signal and power layers are filled out

with ground plane for general noise suppression. To ensure a

low impedance connection between the planes, there are mul-

tiple through-hole connections to the RF ground plane. While

the ground planes on the power and signal planes are used as

general purpose ground returns, any RF grounds related to the

input matching network (e.g., C2) are returned directly to the

RF internal ground plane.

General Operation

The board should be powered by a single supply in the range,

+2.7 V to +5.5 V. The power supply to each of the VPOS pins

is decoupled by a 10

Ω resistor and a 0.1 µF capacitor.

The two signal inputs are ac-coupled using 680 pF high quality

RF capacitors (C1, C2). A 53.6

Ω resistor across the differential

signal inputs (INHI, INLO) combines with the internal 900

Ω

input impedance to give a broadband input impedance of 50.6

Ω.

This termination is not optimal from a noise perspective due to

the Johnson noise of the 53.6

Ω resistor. Neither does it take

account for the AD8313’s reactive input impedance or of the

decrease over frequency of the resistive component of the input

impedance. However, it does allow evaluation of the AD8313

over its complete frequency range without having to design

multiple matching networks.

For optimum performance, a narrowband match can be imple-

mented by replacing the 53.6

Ω resistor (labeled L/R) with an

RF inductor and replacing the 680 pF capacitors with appropri-

ate values. The section on Input Matching includes a table of

recommended values for selected frequencies and explains the

method of calculation.

Switch 1 is used to select between power-up and power-down

modes. Connecting the PWDN pin to ground enables normal

operation of the AD8313. In the opposite position, the PWDN

pin can either be driven externally (SMA connector labeled

EXT ENABLE) to either device state or allowed to float to a

disabled device state.

The evaluation board ships with the AD8313 configured to

operate in RSSI measurement mode, the logarithmic output

appearing on the SMA connector labeled VOUT. This mode is

set by the 0

Ω resistor (R11), which shorts the VOUT and

VSET pins to each other.

Varying the Logarithmic Slope

The slope of the AD8313 can be increased from its nominal

value of 18 mV/dB to a maximum of 40 mV/dB by removing

R11, the 0

Ω resistor, which shorts VSET to VOUT. VSET and

VOUT are now connected through a 20 k

Ω potentiometer.

Operating in Controller Mode

To put the AD8313 into controller mode, R7 and R11 should

be removed, breaking the link between VOUT and VSET. The

VSET pin can then be driven externally via the SMA connector

labeled EXT VSET IN ADJ.

Increasing Output Current

0

Ω and install potentiometer R4 (1 kΩ to 5 kΩ).