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AD8111AST датащи(PDF) 3 Page - Analog Devices

номер детали AD8111AST
подробное описание детали  260 MHz, 16 x 8 Buffered Video Crosspoint Switches
PDF  28 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD8111AST датащи(HTML) 3 Page - Analog Devices

  AD8111AST Datasheet HTML 1Page - Analog Devices AD8111AST Datasheet HTML 2Page - Analog Devices AD8111AST Datasheet HTML 3Page - Analog Devices AD8111AST Datasheet HTML 4Page - Analog Devices AD8111AST Datasheet HTML 5Page - Analog Devices AD8111AST Datasheet HTML 6Page - Analog Devices AD8111AST Datasheet HTML 7Page - Analog Devices AD8111AST Datasheet HTML 8Page - Analog Devices AD8111AST Datasheet HTML 9Page - Analog Devices Next Button
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AD8110/AD8111
–3–
REV. 0
TIMING CHARACTERISTICS (Serial)
Limit
Parameter
Symbol
Min
Typ
Max
Units
Serial Data Setup Time
t1
20
ns
CLK Pulsewidth
t2
100
ns
Serial Data Hold Time
t3
20
ns
CLK Pulse Separation, Serial Mode
t4
100
ns
CLK to
UPDATE Delay
t5
0ns
UPDATE Pulsewidth
t6
50
ns
CLK to DATA OUT Valid, Serial Mode
t7
180
ns
Propagation Delay,
UPDATE to Switch On or Off
–
8
ns
Data Load Time, CLK = 5 MHz, Serial Mode
–
8
µs
CLK,
UPDATE Rise and Fall Times
–
100
ns
RESET Time
–
200
ns
1
0
1
0
1 = LATCHED
0 = TRANSPARENT
DATA OUT
CLK
DATA IN
OUT7 (D4)
OUT7 (D3)
OUT00 (D0)
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t2
t4
t1
t3
t7
t5
t6
UPDATE
Figure 1. Timing Diagram, Serial Mode
Table I. Logic Levels
VIH
VIL
VOH
VOL
IIH
IIL
IOH
IOL
RESET, SER/PAR
RESET, SER/PAR
RESET, SER/PAR
RESET, SER/PAR
CLK, DATA IN,
CLK, DATA IN,
CLK, DATA IN,
CLK, DATA IN,
CE, UPDATE
CE, UPDATE
DATA OUT
DATA OUT
CE, UPDATE
CE, UPDATE
DATA OUT
DATA OUT
2.0 V min
0.8 V max
2.7 V min
0.5 V max
20
µA max
–400
µA min
–400
µA max
3.0 mA min



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