AD8111AST datasheet(16/28 Pages) AD

16 / 28 page

AD8110/AD8111

–16–

REV. 0

This will ensure that the programming matrix is always in a

known state. From then on, parallel programming can be used

to modify a single output or more at a time.

In a similar fashion, if both

CE and UPDATE are taken LOW

after initial power-up, the random power-up data in the shift

to prevent the crosspoint from being programmed into an un-

known state DO NOT APPLY LOW LOGIC LEVELS TO

BOTH

CE AND UPDATE AFTER POWER IS INITIALLY

APPLIED. Programming the full shift register one time to a

desired state by either serial or parallel programming after initial

power-up will eliminate the possibility of programming the

matrix to an unknown state.

To change an output’s programming via parallel programming,

SER/PAR and UPDATE should be taken HIGH and CE should

be taken LOW. The CLK signal should be in the HIGH state.

The address of the output that is to be programmed should be

put on A0–A2. The first four data bits (D0–D3) should contain

the information that identifies the input that is programmed to

the output that is addressed. The fourth data bit (D4) will de-

termine the enabled state of the output. If D4 is LOW (output

disabled), the data on D0–D3 does not matter.

After the desired address and data signals have been established,

they can be latched into the shift register by a HIGH-to-LOW

transition of the CLK signal. The matrix will not be programmed,

however, until the

UPDATE signal is taken low. Thus, it is

possible to latch in new data for several or all of the outputs first

via successive negative transitions of CLK while

UPDATE is

held high, and then have all the new data take effect when

UP-

DATE goes LOW. This technique should be used when pro-

gramming the device for the first time after power-up when

using parallel programming.

POWER-ON RESET

When powering up the AD8110/AD8111 it is usually desirable

to have the outputs come up in the disabled state. The

RESET

pin, when taken LOW will cause all outputs to be in the dis-

abled state. However, the

RESET signal DOES NOT RESET

ALL REGISTERS in the AD8110/AD8111 This is important

when operating in the parallel programming mode. Please refer

to that section for information about programming internal

registers after power-up. Serial programming will program the

entire matrix each time, so no special considerations apply.

Since the data in the shift register is random after power-up, it

should not be used to program the matrix or else the matrix can

enter unknown states. To prevent this, DO NOT APPLY LOGIC

LOW SIGNALS TO BOTH

CE AND UPDATE INITIALLY

AFTER POWER-UP. The shift register should first be loaded

with the desired data, and then

UPDATE can be taken LOW to

program the device.

The

RESET pin has a 20 k

Ω pull-up resistor to DVDD that can

be used to create a simple power-up reset circuit. A capacitor

from

RESET to ground will hold RESET LOW for some time

while the rest of the device stabilizes. The LOW condition will

cause all the outputs to be disabled. The capacitor will then

charge through the pull-up resistor to the HIGH state; thus

allowing full programming capability of the device.

GAIN SELECTION

The 16

× 8 crosspoints come in two versions depending on the

desired gain of the analog circuit paths. The AD8110 device is

unity gain and can be used for analog logic switching and other

applications where unity gain is desired. The AD8110 can also

be used for the input and interior sections of larger crosspoint

arrays where termination of output signals is not usually used.

The AD8110 outputs have a very high impedance when their

outputs are disabled.

For devices that will be used to drive a terminated cable with its

outputs, the AD8111 can be used. This device has a built-in

gain of two that eliminates the need for a gain-of-two buffer to

drive a video line. Because of the presence of the feedback net-

work in these devices, the disabled output impedance is about

1 k

Ω.

If external amplifiers are used to provide a gain = +2, our AD8079

provides a fixed G = +2 function.

CREATING LARGER CROSSPOINT ARRAYS

The AD8110/AD8111 are high density building blocks for cre-

ating crosspoint arrays of dimensions larger than 16

× 8. Various

features such as output disable, chip enable, and gain-of-one-

and-two options are useful for creating larger arrays. For very

large arrays, they can be used along with the AD8116, a 16

× 16

video crosspoint device. In addition, when required for custom-

izing a crosspoint array size, they can be used with the AD8108

and AD8109 a pair (unity gain and gain-of-two) of 8

× 8 video

crosspoint switches.

The first consideration in constructing a larger crosspoint is to

determine the minimum number of devices that are required.

The 16

× 8 architecture of the AD8110/AD8111 contains 128

“points,” which is a factor of 32 greater than a 4

× 1 crosspoint.

The PC board area and power consumption savings are readily

apparent when compared to using these smaller devices.

For a nonblocking crosspoint, the number of points required is

the product of the number of inputs multiplied by the number

of outputs. Nonblocking requires that the programming of a

given input to one or more outputs does not restrict the avail-

ability of that input to be a source for any other outputs.

Some nonblocking crosspoint architectures will require more

than this minimum as calculated above. Also, there are blocking

architectures that can be constructed with fewer devices than

this minimum. These systems have connectivity available on a

statistical basis that is determined when designing the overall

system.

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