AD7883 datasheet(3/12 Pages) AD

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AD7883

REV. 0

–3–

TIMING CHARACTERISTICS1

Limit at +25 C

Limit at TMIN, TMAX

Parameter

(All Versions)

Units

Conditions/Comments

ns min

CONVST

Pulse Width

200

ns max

CONVST

to BUSY Falling Edge

ns min

BUSY

to CS Setup Time

ns min

to RD Setup Time

ns min

to RD Hold Time

110

150

ns min

Pulse Width

100

140

ns max

Data Access Time after RD

ns min

Bus Relinquish Time after RD

ns max

NOTES

1Timing specifications in bold print are 100% production tested. All other times are sample tested at +25

°C to ensure compliance. All input signals are specified with

tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

7 is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.

8 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapo-

lated back to remove the effects of charging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of

the part and as such is independent of external bus loading capacitances.

(VSS = +3 V to +3.6 V, VREF = VDD, AGND = DGND = 0 V)

DB0 – DB11

DATA

VALID

tCONVERT

CONVST

BUSY

THREE-STATE

TRACK/HOLD

GOES INTO HOLD

Figure 1. Timing Diagram

OUTPUT

0.8mA

+1.6V

200

µA

50pF

Figure 2. Load Circuit for Access and Relinquish Time

Table I. Truth Table

CONVT

Function

Not Selected

Start Conversion

Enable ADC Data

Data Bus Three Stated

ORDERING GUIDE

Model

Temperature Range

Package Option*

AD7883BN

–40

°C to +85°C

N-24

AD7883BR

–40

°C to +85°C

R-24

*N = Plastic DIP; R = SOIC (Small Outline Integrated Circuit).

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