AD7856ARS datasheet(29/32 Pages) AD

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AD7856

–29–

REV. A

68HC11/L11/16

SCK

AD7856

CONVST

CLKIN

SCLK

DIN

SYNC

OPTIONAL

4MHz/6MHz

BUSY

IRQ

MASTER

SLAVE

OPTIONAL

DOUT

MISO

MOSI

SPI

DVDD

HC16, QSPI

Figure 38. 68HC11 and 68HC16 Interface

AD7856 to ADSP-21xx Interface

Figure 39 shows the AD7856 interface to the ADSP-21xx. The

ADSP-21xx is the master and the AD7856 is the slave. The

AD7856 is in Interface Mode 2. For the ADSP-21xx the bits in

the serial port control register should be set up as TFSR = RFSR

= 1 (need a frame sync for every transfer), SLEN = 15 (16-bit

word length), TFSW = RFSW = 1 (alternate framing mode for

transmit and receive operations), INVRFS = INVTFS = 1

(active low RFS and TFS), IRFS = 0, ITFS = 1 (External RFS

and internal TFS), and ISCLK = 1 (internal serial clock). The

CLKIN and

CONVST signals can be supplied from the ADSP-

21xx or from an external source. The serial clock from the

ADSP-21xx must be inverted before the SCLK pin of the

AD7856. This SCLK could also be used to drive the CLKIN

input of the AD7856. The BUSY signal indicates when the

conversion is finished and may not be required. The data access

and hold times of the ADSP-21xx and the AD7856 allow for a

serial clock of 6 MHz at 5 V.

ADSP-21xx

AD7856

CONVST

CLKIN

DOUT

DIN

SYNC

OPTIONAL

4MHz/6MHz

BUSY

IRQ

MASTER

SLAVE

TFS

SCK

SCLK

RFS

OPTIONAL

Figure 39. ADSP-21xx Interface

AD7856 to DSP56000/1/2/L002 Interface

Figure 40 shows the AD7856 to DSP56000/1/2/L002 interface.

Here the DSP5600x is the master and the AD7856 is the slave.

The AD7856 is in Interface Mode 2. The setting of the bits in

the registers of the DSP5600x would be for synchronous opera-

tion (SYN = 1), internal frame sync (SCD2 = 1), gated internal

clock (GCK = 1, SCKD = 1), 16-bit word length (WL1 = 1,

WL0 = 0). Since a gated clock is used here the SCLK cannot be

tied to the CLKIN of the AD7856. The SCLK from the DSP5600x

must be inverted before it is applied to the AD7856. Again the

data access and hold times of the DSP5600x and the AD7856

allows for a SCLK of 6 MHz, VDD = 5 V.

DSP56000/1/2/L002

SRD

AD7856

CONVST

CLKIN

SCLK

DIN

SYNC

OPTIONAL

BUSY

IRQ

MASTER

SLAVE

OPTIONAL

DOUT

SC2

STD

SCK

4MHz/6MHz

Figure 40. DSP56000/1/2/L002 Interface

APPLICATION HINTS

Grounding and Layout

The analog and digital supplies to the AD7856 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The part has very good

immunity to noise on the power supplies as can be seen by the

PSRR vs. Frequency graph. However, care should still be taken

with regard to grounding and layout.

The printed circuit board that houses the AD7856 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be easily separated. A minimum

etch technique is generally best for ground planes as it gives the

best shielding. Digital and analog ground planes should only be

joined in one place. If the AD7856 is the only device requiring

an AGND to DGND connection, the ground planes should

be connected at the AGND and DGND pins of the AD7856. If

the AD7856 is in a system where multiple devices require AGND

to DGND connections, the connection should still be made at

one point only, a star ground point that should be established

as close as possible to the AD7856.

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