AD7835AS datasheet(11/16 Pages) AD

11 / 16 page

AD7834/AD7835

REV. A

–11–

VOUT has been disconnected from the DSG pin by the opening

of G5 but will track the voltage present at DSG via the unity

gain buffer.

Power-On with LDAC Low, CLR High

In many applications of the AD7834/AD7835 LDAC will be

kept continuously low, thus updating the DAC after each valid

data transfer. If LDAC is low when power is applied, then G1 is

closed and G2 is open, thus connecting the output of the DAC

to the input of the output amplifier. G3 and G5 will be closed

and G4 and G6 open, connecting the amplifier as a unity gain

buffer, as before. VOUT is connected to DSG via G5 and R (a

thin film resistance between DSG and VOUT) until VDD and VSS

reach approximately

±10 V. Then, the internal power-on cir-

cuitry opens G3 and G5 and closes G4 and G6. This is the situa-

tion shown in Figure 18. VOUT is now at the same voltage as the

DAC output.

DAC

VOUT

DSG

Figure 18. Output Stage with LDAC Low

Loading the DAC and Using the CLR Input

When LDAC goes low, it closes G1 and opens G2 as in Fig-

ure 18. The voltage at VOUT now follows the voltage present at

the output of the DAC. The output stage remains connected in

this manner until a CLR signal is applied. Then the situation

reverts to that shown in Figure 17. Once again VOUT remains at

the same voltage as DSG until LDAC goes low. This recon-

nects the DAC output to the unity gain buffer.

DSG Voltage Range

During power-on, the VOUT pins of the AD7834/AD7835 are

connected to the relevant DSG pins via G6 and the thin film re-

sistor, R. The DSG potential must obey the max ratings at all

times. Thus, the voltage at DSG must always be within the

range VSS – 0.3 V, VDD + 0.3 V. However, in order that the volt-

ages at the VOUT pins of the AD7834/AD7835 stay within

±2 V of the relevant DSG potential during power-on, the

voltage applied to DSG should also be kept within the range

AGND – 2 V, AGND + 2 V.

Once the AD7834/AD7835 has powered on and the on-chip

amplifiers have settled, the situation is as shown as in Figure 17.

Any voltage that is now applied to the DSG pin is buffered by

the same amplifier that buffers the DAC output voltage in nor-

mal operation. Thus, for specified operation, the maximum

voltage that can be applied to the DSG pin increases to the

maximum allowable VREF(+) voltage, and the minimum voltage

that can be applied to DSG is the minimum VREF(–) voltage. After

the AD7834/AD7835 has fully powered on, the outputs can

track any DSG voltage within this minimum/maximum range.

POWER-ON OF THE AD7834/AD7835

Power should normally be applied to the AD7834/AD7835 in

the following sequence: first VDD and VSS, then VCC, then

VREF(+) and VREF(–).

CONTROLLED POWER-ON OF THE OUTPUT STAGE

A block diagram of the output stage of the AD7834/AD7835 is

shown in Figure 15. It is capable of driving a load of 10 k

Ω in

parallel with 200 pF. G1 to G6 are transmission gates that are

used to control the power on voltage present at VOUT. G1 and

G2 are also used in conjunction with the CLR input to set VOUT

to the user defined voltage present at the DSG pin.

DAC

VOUT

DSG

Figure 15. Block Diagram of AD7834/AD7835 Output Stage

Power-On with CLR Low, LDAC High

The output stage of the AD7834/AD7835 has been designed to

allow output stability during power-on. If CLR is kept low dur-

ing power-on, then just after power is applied to the part, the

situation is as depicted in Figure 16. G1, G4 and G6 are open

while G2, G3 and G5 are closed.

DAC

VOUT

DSG

Figure 16. Output Stage with VDD < 10 V

VOUT is kept within a few hundred millivolts of DSG via G5 and

R. R is a thin-film resistor between DSG and VOUT. The out-

put amplifier is connected as a unity gain buffer via G3 and the

DSG voltage is applied to the buffer input via G2. The amplifi-

ers output is thus at the same voltage as the DSG pin. The out-

put stage remains configured as in Figure 16 until the voltage at

VDD and VSS reaches approximately

±10 V. By now the output

amplifier has enough headroom to handle signals at its input

and has also had time to settle. The internal power-on circuitry

opens G3 and G5 and closes G4 and G6. This situation is shown

in Figure 17. Now the output amplifier is connected in unity

gain mode via G4 and G6. The DSG voltage is still applied to

the noninverting input via G2. This voltage appears at VOUT.

DAC

VOUT

DSG

Figure 17. Output Stage with VDD > 10 V and CLR Low

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