AD7701ARS datasheet(5/16 Pages) AD

5 / 16 page

–5–

REV. D

AD7701

TIMING CHARACTERISTICS

1, 2

Limit at TMIN, TMAX

Parameter

(A, B Versions)

(S, T Versions)

Units

Conditions/Comments

fCLKIN

3, 4

200

kHz min

Master Clock Frequency: Internal Gate Oscillator

MHz max Typically 4.096 MHz

200

kHz min

Master Clock Frequency: Externally Supplied

MHz max

ns max

Digital Output Rise Time. Typically 20 ns

ns max

Digital Output Fall Time. Typically 20 ns

ns min

SC1, SC2 to CAL High Setup Time

ns min

SC1, SC2 Hold Time After CAL Goes High

1000

ns min

SLEEP

High to CLKIN High Setup Time

SSC Mode

3/fCLKIN

ns max

Data Access Time (CS Low to Data Valid)

100

ns max

SCLK Falling Edge to Data Valid Delay (25 ns typ)

250

ns min

MSB Data Setup Time. Typically 380 ns

300

ns max

SCLK High Pulse Width. Typically 240 ns

790

ns max

SCLK Low Pulse Width. Typically 730 ns

l/fCLKIN +200

ns max

SCLK Rising Edge to Hi-Z Delay (l/fCLKIN + 100 ns typ)

t10

8, 9

(4/fCLKIN) +200

ns max

High to Hi-Z Delay

SEC Mode

fSCLK

MHz

Serial Clock Input Frequency

t11

ns min

SCLK Input High Pulse Width

t12

160

ns min

SCLK Low Pulse Width

t13

7, 10

160

ns max

Data Access Time (CS Low to Data Valid). Typically 80 ns

t14

150

ns max

SCLK Falling Edge to Data Valid Delay. Typically 75 ns

t15

250

ns max

High to Hi-Z Delay

t16

200

ns max

SCLK Falling Edge to Hi-Z Delay. Typically 100 ns

AC Mode

t17

ns min

Setup Time. Typically 20 ns

t18

180

ns max

Data Delay Time. Typically 90 ns

t19

200

ns max

SCLK Falling Edge to Hi-Z Delay. Typically 100 ns

NOTES

11Sample tested at +25

°C to ensure compliance. All input signals are specified with t

r = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

12See Figures 1 to 6.

13CLKIN Duty Cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can

draw higher current than specified and possibly become uncalibrated.

14The AD7701 is production tested with f

CLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.

15Specified using 10% and 90% points on waveform of interest.

16In order to synchronize several AD7701s together using the SLEEP pin, this specification is met.

17t

4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

18t

9, t10, t15 and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is

then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the

true bus relinquish time of the part and as such as independent of external bus loading capacitance.

19If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.

10If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as

great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than

4 CLKIN cycles plus 160 ns after CS goes low.

11SDATA is clocked out on the falling edge of the SCLK input.

(AVDD = DVDD = +5 V

10%; AVSS = DVSS = –5 V

10%; AGND = DGND = O V;

fCLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD)

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